Výsledky vyhledávání - "Young Sub You"

Ge Implantation to Improve Crystallinity and Productivity for Solid Phase Epitaxy Prepared by Atomic Mass Unit Cross Contamination-Free Technique

Autor: Chang Hun Lee, Ju Hee Noh, Hyeon Deok Lee, Young Sub You, Seok Jae Kim, Kong Soo Lee, Yong Woo Hyung, Gil Hwan Son, Daehan Yoo, Jae Jong Han, Yong Kwon Kim

Publikováno v: Japanese Journal of Applied Physics. 45:L1193-L1196

Germanium (Ge) ion implantation was investigated for crystallinity enhancement during solid phase epitaxial (SPE) regrowth. Electron back-scatter diffraction (EBSD) measurement showed numerical increase of 19% of (100) signal, which might be due to t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2547d8a425a81e40f7be241827c62f43
https://doi.org/10.1143/jjap.45.l1193

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Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

Autor: Cheol-kyu Lee, Eun Ha Lee, Jong-Ho Lee, Hionsuck Baik, Mong sub Lee, Youngsu Chung, Nae-In Lee, Sung Kee Han, Ho-Kyu Kang, Yun Ki Choi, Young-Sub You, Hyung-Suk Jung, Hajin Lim, Jong-Bong Park

Publikováno v: 2007 IEEE Symposium on VLSI Technology.

We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer(c-ML)/AlOx/TaN/HfON stacks for

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::addd3f2b638b2d9f05be693ff9c4b954
https://doi.org/10.1109/vlsit.2007.4339690

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Highly Manufacturable Single Metal Gate Process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

Autor: Cheol-kyu Lee, Min-Joo Kim, Jong-Ho Lee, Hyung-Suk Jung, Young-Sub You, Young Su Chung, Ho-Kyu Kang, Hionsuck Baik, Hajin Lim, Sung Kee Han, Mong sub Lee, Nae In Lee, Eunha Lee

Publikováno v: 2006 International Electron Devices Meeting.

The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are careful

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a2b4619b61ccca2ba78077b45f374fbb
https://doi.org/10.1109/iedm.2006.346860

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Dual High-k Gate Dielectric Technology Using Selective AlOx Etch (SAE) Process with Nitrogen and Fluorine Incorporation

Autor: Cheol-kyu Lee, Jong-Ho Lee, Youngsu Chung, Hionsuck Baik, Yunseok Kim, Nae-In Lee, Hajin Lim, Seul-Gi Kim, Ho-Kyu Kang, Min-Joo Kim, Young-Sub You, Mi Young Yu, Mong sub Lee, Sung Kee Han, Hyung-Suk Jung

Publikováno v: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

We propose a novel Vth, control method for HfSiON (or HfO2) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlOx etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nM

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::290527b97d90facc5eeb35d38d03da8b
https://doi.org/10.1109/vlsit.2006.1705267

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Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Autor: Joo-On Park, Byung-Gook Park, Jae Sung Sim, Kyung Rok Kim, Jong Duk Lee, Yong Kyu Lee, Ki-Whan Song, You Seung Jin, Young-Wug Kim, Young Sub You

Publikováno v: Japanese Journal of Applied Physics. 44:2618

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::eae607aaf613dbb2b560586ad0315947
https://doi.org/10.1143/jjap.44.2618

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