Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Yoshiro Tsuboi"'
Autor:
Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2957-2965
We have developed an eight-core media processor for mobile multimedia applications, which achieves low power consumption and high performance. The processor uses a specific parallel process execution scheme that achieves high performance and allows p
Autor:
Tomoo Yamakage, N. Matsumoto, T. Kitazawa, Shunichi Ishiwata, Takayoshi Shimazawa, Masataka Matsui, S. Michinaka, M. Saito, Hideki Takeda, Yoshiro Tsuboi, Takashi Miyamori, G. Ootomo, T. Kamei, A. Oue, K. Yahagi, T. Kodama
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:530-540
A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute
Autor:
Tadahiro Kuroda, M. Hamada, T. Terazawa, F. Sano, H. Momose, Yoshiro Tsuboi, M. Takahashi, Kojiro Suzuki, A. Chiba, T. Fujita, Tohru Furuyama, Kimiyoshi Usami, Mutsunori Igarashi, Masahiro Kanazawa, Tsuyoshi Nishikawa, Fumitoshi Hatori, Takashi Ishikawa, Shinji Mita, Yohji Watanabe, Hideho Arakida
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1772-1780
A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit r
Autor:
T. Fujita, Fumiyuki Yamane, Hiroyuki Usui, Hiroyuki Hara, Fumihiko Tachibana, Takahiro Yamashita, Mototsugu Hamada, Yoshiro Tsuboi, Shuou Nomura, Yukimasa Miyamoto, Chen Kong Teh
Publikováno v:
2009 IEEE International Conference on IC Design and Technology.
A multi-core co-processor for mobile application processors is introduced. It provides low-power, high-throughput, fully software-based acceleration of multimedia processing. The test chip fabricated in a 65nm CMOS technology consumes 620mW in H.264
Autor:
H. Sato, Takahiro Yamashita, S. Matsumoto, Fumiyuki Yamane, Yoshiro Tsuboi, Yohji Watanabe, Hiroyuki Hara, Fumihiko Tachibana, K. Seki, M. Hamada, Shuou Nomura, Takeshi Kitahara
Publikováno v:
CICC
A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with sma
Autor:
Takashi Miyamori, K. Seki, Masato Uchiyama, S. Matsumoto, Fumiyuki Yamane, Yohji Watanabe, C. Kumtornkittikul, Jun Tanabe, M. Takahashi, Shuou Nomura, Hiroyuki Usui, Takahiro Yamashita, H. Sato, Y. Homma, Takeshi Kitahara, Yoshiro Tsuboi, Fumihiko Tachibana, M. Hamada, Yukimasa Miyamoto, Chen Kong Teh, Hiroyuki Hara, T. Fujita
Publikováno v:
ISSCC
A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages,
Autor:
Tohru Furuyama, K. Ohmori, Hideho Arakida, Toshihide Fujiyoshi, M. Koana, Hideaki Yamamoto, Hiroshi Nakamura, M. Takahashi, Tsuyoshi Nishikawa, Yoshiro Tsuboi, T. Terazawa, E. Watanabe, T. Fujita, Y. Kitasho, T. Aikawa, H. Ando, Yuji Ueda, Manabu Watanabe
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
A single-chip MPEG-4 audiovisual LSI in a 0.13 /spl mu/m 5M CMOS technology with 16 Mb embedded DRAM is presented. Four 16 b RISC processors and dedicated hardware accelerators including a 5 GOPS post filtering engine are integrated on the IC. The ch
Autor:
Hideki Takeda, Masataka Matsui, N. Matsumoto, Tomoo Yamakage, Takayoshi Shimazawa, T. Kodama, Shunichi Ishiwata, S. Michinaka, T. Kitazawa, G. Ootomo, K. Yahagi, Takashi Miyamori, Yoshiro Tsuboi, T. Kamei, A. Oue
Publikováno v:
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tas
Publikováno v:
Concrete Journal. 19:21-29