Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Yoshiki Kawajiri"'
Autor:
Keita Matsuoka, Ryosuke Sato, Yuki Matsukura, Yoshiki Kawajiri, Hiromi Iino, Naoyuki Nozawa, Kyomi Shibata, Yuki Kondo, Shinobu Satoh, Masashi Asahina
Publikováno v:
Communications Biology, Vol 4, Iss 1, Pp 1-12 (2021)
Matsuoka et al. study the mechanism by which transcription factors ANAC071 and ANAC096 promotes regeneration of wounded tissue in Arabidopsis by mutagenesis and morphological characterization. They find that these factors are essential for wound-indu
Externí odkaz:
https://doaj.org/article/f9beafae4df1496caeae21a1d2fbdf2c
Autor:
Ryosuke Sato, Hiromi Iino, Yuki Matsukura, Yuki Kondo, Naoyuki Nozawa, Kyomi Shibata, Masashi Asahina, Shinobu Satoh, Yoshiki Kawajiri, Keita Matsuoka
Publikováno v:
Communications Biology
Communications Biology, Vol 4, Iss 1, Pp 1-12 (2021)
Communications Biology, Vol 4, Iss 1, Pp 1-12 (2021)
ANAC071 and its homolog ANAC096 are plant-specific transcription factors required for the initiation of cell division during wound healing in incised Arabidopsis flowering stems and Arabidopsis hypocotyl grafts; however, the mechanism remains mostly
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4a2769bdd71d4b5e5b33a7ef7252c169
https://pubmed.ncbi.nlm.nih.gov/33742091
https://pubmed.ncbi.nlm.nih.gov/33742091
Autor:
Masaaki Mihara, Yoshiki Kawajiri, K. Kobayashi, Taku Ogura, Moriyoshi Nakashima, N. Ajika, Shoji Shukuri, S. Shimizu, H. Otoi
Publikováno v:
2014 IEEE 6th International Memory Workshop (IMW).
This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabrica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b83d30120a038f6910ecc298502c053
https://doi.org/10.1109/imw.2014.6849386
https://doi.org/10.1109/imw.2014.6849386
Autor:
Masashi Wada, T. Hayasaka, H. Sonoyama, H. Makimoto, Yoshiki Kawajiri, T. Omae, O. Ishizaki, Yoshikazu Miyawaki, F. Niita, Masaaki Mihara, H. Kimura, K. Kobayashi, J. Etoh, S. Shimizu, T. Inaba, Y. Okihara
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:1551-1556
1.8 V-only 16 Mb CMOS divided-bit line-NOR (DINOR) flash memory with alternating background-operation (BGO) capability has 72 ns random access time. The EGO feature allows program or erase in one bank while the device simultaneously allows read in th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::735191c460e0ecb2e96691e52ea54af3
https://doi.org/10.1109/4.799862
https://doi.org/10.1109/4.799862
Autor:
Goro Kitsukawa, Takesada Akiba, Takayuki Kawahara, Masashi Horiguchi, Tokuo Kure, Yoshiki Kawajiri, Mayu Aoki
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:715-722
A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 /spl mu/m technology. After amplification in one array, the charges in t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ca05d879726f0c43ddba418f756af05
https://doi.org/10.1109/4.293118
https://doi.org/10.1109/4.293118
Autor:
Takashi Nishida, Ryo Nagai, Toshikazu Tachibana, Shoji Shukuri, Mayu Aoki, Takesada Akiba, Tokuo Kure, T. Sakai, Yuzuru Ohji, Hiroki Yamashita, Takayuki Kawahara, Goro Kitsukawa, Norio Hasegawa, Yasushi Kawase, T. Kisu, Kazuhiko Sagara, Masashi Horiguchi, Yoshiki Kawajiri, Natsuki Yokoyama
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:1105-1113
256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the sub
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9d73d021ef7a93733c52392d287555d
https://doi.org/10.1109/4.245589
https://doi.org/10.1109/4.245589
Autor:
Takesada Akiba, Goro Kitsukawa, Masakazu Aoki, Takayuki Kawahara, Kiyoo Itoh, Yoshiki Kawajiri, Takeshi Sakata
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:816-823
A high-speed small-area DRAM sense amplifier with a threshold-voltage (V/sub T/) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::939f0cece2338d5988d131132677f4ca
https://doi.org/10.1109/4.222181
https://doi.org/10.1109/4.222181
Autor:
Tokuo Kure, Yoshiki Kawajiri, Mayu Aoki, Takayuki Kawahara, Masashi Horiguchi, Goro Kitsukawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:1136-1144
Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a sw
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24722cc9b675805139dec2a9ff8eec73
https://doi.org/10.1109/4.245594
https://doi.org/10.1109/4.245594
Autor:
Takesada Akiba, Yoshiki Kawajiri, Takayuki Kawahara, S. Kato, Yoshifumi Kawamoto, Yasushi Kawase, Kazuhiko Sagara, Goro Kitsukawa, K. Itoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:589-596
A 0.3- mu m sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V/sub cc/ connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6244798369f6c606cb243dfa6aee0307
https://doi.org/10.1109/4.126548
https://doi.org/10.1109/4.126548
Autor:
Masayuki Nakamura, Kazuyuki Miyazawa, Takesada Akiba, Yoshiki Kawajiri, Goro Kitsukawa, Kazumasa Yanagisawa, Kiyoo Itoh
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 75:89-102
This paper describes an experimental 1.3-μm, 1-Mb BiCMOS DRAM, the first DRAM to use an ECL interface. The results are as follows: (1) quantitative analysis shows that direct sensing of a small read-signal voltage on the data lines before amplificat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9b6804a5a95bd52109546d0437d15ad
https://doi.org/10.1002/ecjb.4420750509
https://doi.org/10.1002/ecjb.4420750509