Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Yoshihisa Matsubara"'
Autor:
Kazuyuki Matsumaro, Hiroshi Yamashita, Hiroshi Sakaue, Eiichi Soda, Yoshihisa Matsubara, Fumihiro Koba, Nobuyuki Iriki, Takashi Ishigami, Tadayoshi Watanabe, Kaoru Koike, Hiroshi Arimoto
Publikováno v:
Japanese Journal of Applied Physics. 45:5418-5422
In this paper we showed electron projection lithography (EPL) applicability to via formation in a back-end-of-line (BEOL) process for 45-nm technology node through fabricating a two-layer metallization device. We developed a single-layer via-resist p
Autor:
Yoshihisa Matsubara, Takashi Nasuno, Wataru Wakamiya, Eiichi Soda, N. Kobayashi, Akiyuki Minami, Hiroshi Tsuda, Hiromasa Kobayashi, Koichiro Tsujita
Publikováno v:
IEICE Transactions on Electronics. :796-803
A novel via chain structure for failure analysis at 65 nm-node fixing OPC using inner and outer via chain dummy patterns has been proposed. The inner dummy is necessary to localize failure site in 200 nm pitch via chain using an optical beam induced
Publikováno v:
Thin Solid Films. 270:537-543
The effects of Ti film thickness and rapid thermal annealing (RTA) ambient on the properties of narrow TiSi 2 lines were studied. Decreasing the Ti film thickness improves the critical line width of silicidation. Excessive nitridation suppresses the
Publikováno v:
Hyomen Kagaku. 16:233-237
LSI製造に用いられるシリサイドプロセスでは, 固相反応によりセルフアライン構造を形成できることが大きなメリットになっている。このセルフアライン構造にシリサイドを形成する方
Publikováno v:
The journal of physical chemistry. B. 109(21)
The effect of neurite outgrowth of PC12 cells on collagen-coated glass plates under intermittent light irradiation at 525 nm and 0.4 mW/cm2 of intensity was investigated. Neurite outgrowth of PC12 cells was significantly suppressed when PC12 cells we
Autor:
Hiroshi Arimoto, Naoki Yamashita, Tadayoshi Watanabe, Fumihiro Koba, Yoshihisa Matsubara, Daisuke Kawana, Seiichi Tagawa, Eiichi Soda, Mitsuru Sato, Kazuyuki Matsumaro, Yasushi Fujii, Takahiro Kozawa, Tasuku Matsumiya, Katsumi Ohmori
Publikováno v:
SPIE Proceedings.
In this study, we have demonstrated a resist process to fabricate sub 45-nm lines and spaces (L&S) patterns (1:1) by using electron projection lithography (EPL) for a back-end-of-line (BEOL) process for 45-nm technology node. As a starting point we t
Publikováno v:
2006 IEEE International Reliability Physics Symposium Proceedings.
Via chain resistance categorized by OBIRCH image was investigated using samples having 140nm and 200nm pitch via chain interconnect. Via chain resistance is increased with an increasing number of defects in the case of line edge roughness failures. L
Autor:
Toshiyuki Ishimaru, Takuya Hagiwara, Yoshihisa Matsubara, Kiyoshi Fujii, Seiji Matsuura, Wataru Wakamiya
Publikováno v:
Optical Microlithography XVIII.
The FPA-5800FS1 157-nm scanner installed at Selete has demonstrated a minimum resolution of 55 nm for line-and-space (L/S) patterns with a numerical aperture (NA) of 0.8. The scanner has been used for 65-nm-node device fabrication and will be used fo
Publikováno v:
SPIE Proceedings.
We developed a process monitoring system that calculates the effective dose and focus of device wafers using an overlay metrology tool. The effective dose is monitored by measuring the overall width of the fine line-and-space (LS) patterns, the duty
Publikováno v:
SPIE Proceedings.
Pattern placement error (PPE) of device pattern and overlay mark does not necessarily coincide. So it is important to measure PPE of device pattern accurately for optimizing overlay mark design. But it has been hard. To resolve this problem a new met