Zobrazeno 1 - 10
of 96
pro vyhledávání: '"Yoshiaki Toyoshima"'
Autor:
Hiroyoshi Tanimoto, Yoshiaki Sugizaki, Akihiro Kajita, Yoshiaki Toyoshima, Nobutoshi Aoki, Makoto Wada, Hideki Shibata, Takashi Kurusu, Atsunobu Isobayasi
Publikováno v:
Hyomen Kagaku. 35:250-255
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8032830f6834d804e63e92f4929b4ca2
https://doi.org/10.1380/jsssj.35.250
https://doi.org/10.1380/jsssj.35.250
Autor:
Takeshi Sonehara, Akira Hokazono, Hiroshi Uchida, Yoshiaki Toyoshima, Satoshi Inaba, Mitsuhiro Tomita, H. Akutsu, Shigeru Kawanaka, T. Sasaki
Publikováno v:
IEEE Transactions on Electron Devices. 58:3778-3786
Platinum (Pt) incorporation into nickel silicide (NiSi) films improves silicide characteristics such as lower contact resistance RC at silicide/Si interface and higher thermal stability. The impact of Pt incorporation is widely accepted and recognize
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71a8671212ac8b1d8d5f644ed78526ba
https://doi.org/10.1109/ted.2011.2166557
https://doi.org/10.1109/ted.2011.2166557
Autor:
Yoshiaki Toyoshima, Ichiro Mizushima, Shigeru Kawanaka, Akira Hokazono, Naoki Kusunoki, Satoshi Inaba, Hiroshi Itokawa
Publikováno v:
IEEE Transactions on Electron Devices. 58:1302-1310
Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::900b931ec76b64f6b8210bde88e06b76
https://doi.org/10.1109/ted.2011.2112770
https://doi.org/10.1109/ted.2011.2112770
Autor:
Naoki Kusunoki, Yoshiaki Toyoshima, Atsushi Azuma, Shigeru Kawanaka, Ichiro Mizushima, T. Ishida, K. Adachi, Akira Hokazono, Hiroki Okamoto, Nobuaki Yasutake, Kiyotaka Miyano, Hiroshi Itokawa
Publikováno v:
Solid-State Electronics. 53:712-716
In general, closer proximity of embedded SiGe (eSiGe) source drain (S/D) structure to the channel improves p-channel metal oxide semiconductor field-effect transistor (pMOSFET) performance because of the higher stress in the channel. However, we foun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::709feddaba6581e7b5037e040562df40
https://doi.org/10.1016/j.sse.2009.02.018
https://doi.org/10.1016/j.sse.2009.02.018
Autor:
Masaki Kondo, M. Fujiwara, Yoshiaki Toyoshima, Shigeru Kawanaka, Shintaro Okamoto, K. Adachi, Hiroshi Itokawa, Akira Hokazono, Hiroki Okamoto, Atsushi Azuma, Nobutoshi Aoki, H. Tsujii, T. Ishida, Nobuaki Yasutake
Publikováno v:
Japanese Journal of Applied Physics. 47:2564-2568
The impacts of source and drain (S/D) doping on device performance in embedded SiGe (e-SiGe) p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET) are presented. An in situ boron-doped e-SiGe S/D device exhibits higher drive curre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20bd289908500ce861af303f26331e51
https://doi.org/10.1143/jjap.47.2564
https://doi.org/10.1143/jjap.47.2564
Autor:
Yoshiaki Toyoshima, Kazuya Ohuchi, T. Morooka, Ichiro Mizushima, Naoki Kusunoki, Shigeru Kawanaka, S. Mori, Nobuaki Yasutake, Atsushi Azuma, Nobutoshi Aoki, T. Ishida
Publikováno v:
Solid-State Electronics. 51:1437-1443
A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c6141933fa9bfaab7bfeb15d1c38d1c
https://doi.org/10.1016/j.sse.2007.09.034
https://doi.org/10.1016/j.sse.2007.09.034
Autor:
Atsushi Azuma, Kenji Kojima, Yoshiaki Toyoshima, Koji Nagatomo, Mariko Takayanagi, Shigeru Kawanaka, T. Watanabe, Motoyuki Sato, Katsuyuki Sekine
Publikováno v:
Japanese Journal of Applied Physics. 46:3185-3188
A threshold voltage lowering of up to 400 mV in HfSiON/polycrystalline silicon (poly-Si) gate stack p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) by fluorine incorporation into the channel is observed. Physical analysis ver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c763f64b714e77c70350457786e6b248
https://doi.org/10.1143/jjap.46.3185
https://doi.org/10.1143/jjap.46.3185
Autor:
Hirofumi Yamashita, H. Ootani, R. Hasumi, K. Honda, Yoshiaki Toyoshima, K. Eda, A. Mochizuki, Tatsuya Ohguro, Yoshitaka Egawa, T. Asami, Hiroki Sasaki, Hisayo Momose, Y. Sugiura
Publikováno v:
SPIE Proceedings.
Back Side Illumination (BSI) CMOS image sensors with two-layer photo detectors (2LPDs) have been fabricated and evaluated. The test pixel array has green pixels (2.2um x 2.2um) and a magenta pixel (2.2um x 4.4um). The green pixel has a single-layer p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::780f4d788585f6b24cd308ca1fda0376
https://doi.org/10.1117/12.2077122
https://doi.org/10.1117/12.2077122
Autor:
M. Inohara, Yoshiaki Toyoshima
Publikováno v:
IEEE Transactions on Electron Devices. 52:2634-2639
The demand for higher current density in metal interconnects continues to increase to meet the challenges of higher operation frequency and the more complex design requirement of deep submicrometer integrated circuits. However, improvement in the all
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b20997082c43578a1cf42f4ca52e9592
https://doi.org/10.1109/ted.2005.859640
https://doi.org/10.1109/ted.2005.859640
Autor:
Kiyotaka Miyano, Y. Tsunashima, Satoshi Inaba, Yoshiaki Toyoshima, Kazuya Ohuchi, Ichiro Mizushima, Hidemi Ishiuchi, Hisato Oyamatsu, Akira Hokazono, Kazunari Ishimaru, Hajime Nagano
Publikováno v:
IEEE Transactions on Electron Devices. 51:1401-1408
In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel regio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a61925271369626c199dae88474f32e
https://doi.org/10.1109/ted.2004.833573
https://doi.org/10.1109/ted.2004.833573