Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Yongjik Park"'
Publikováno v:
Microelectronic Engineering. 119:32-36
We realized Sphere-shaped-recess-cell-array-transistor to improve short channel effect.Negative shift of threshold voltage and increase of swing were observed after FN stress.The degradation was improved by small grain sized gate electrode and radica
Publikováno v:
International Symposium for Testing and Failure Analysis.
In this paper, we investigate that Gate-Induced Drain Leakage (GIDL)-weak cells can be screened effectively by modulation of cell-plate voltage (VPlate) during retention time in dynamic random access memory (DRAM) with Negative Wordline bias scheme (
Autor:
Kweonjae Lee, Joosung Lee, Tae-Heon Kim, Aeran Hong, Daehan Han, Yongjik Park, Yong-Hyeon Kim, Yun-Hye Chu
Publikováno v:
Design for Manufacturability through Design-Process Integration VI.
As semiconductor process technology scales down to sub 30nm process node and beyond dimensions, the printability and process window of the lithographic patterns are seriously reduced due to the fundamental limit of the lithography and process variati
Autor:
Se-Chung Oh, Chilhee Chung, Keon-Soo Kim, J.H. Park, Yongjik Park, Yong-Jun Lee, Jung-hyeon Kim, Hong-Hyun Park, S. Choi, S.O. Park, H. K. Kang, Yung-Sang Kim, Sungho Park, Woojin Kim, Hong-jae Shin, JoonMyoung Lee, Hyung-Shin Kwon, Joo-Hyun Jeong, W. C. Lim, Hyoshin Ahn, Kyoung-Soo Kim
Publikováno v:
2011 International Electron Devices Meeting.
In this article, we report the first experimental demonstration of sub-20nm MTJ cells for investigating the downscaling feasibility of spin-transfer torque (STT) MRAM, one of the most promising candidates to replace conventional memories. We demonstr
Autor:
Daehan Han, Yoon-Min Kim, Aeran Hong, In-Ho Nam, Hong-Ji Lee, Min-Chul Han, Kyungseok Oh, Yongjik Park, Yong-Hyeon Kim, Tae Heon Kim
Publikováno v:
SPIE Proceedings.
Semiconductor industry has been experiencing rapid and continuous shrinkage of feature size along with Moore's law. As the VLSI technology scales down to sub 40nm process node. Control of critical dimension (CD) and Extraction of Unanticipated weak p
Autor:
Woo-Tag Kang, Kang-Yoon Lee, Jeong-Seok Kim, Jong-Woo Park, Yoo-Cheol Shin, Tae-Heon Kim, Yongjik Park
Publikováno v:
IEEE Electron Device Letters. 21:9-11
The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 /spl Aring/ have been studied. In order to minimize the junction leakage current, the thickness of the CoSi/sub 2/ layer should he controlled un
Autor:
S.Y. Lee, Suk-Ho Joo, Kyung-Seop Kim, H. J. Joo, D. J. Jung, N. W. Jang, Yongjik Park, Kyu-han Lee, Soon-Rewl Lee, Ho-Jung Kim, Yoon-Jong Song, S.O. Park, Sang-Wan Nam
Publikováno v:
2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C
Autor:
S.O. Park, Yongjik Park, Kinam Kim, Seung-Kyu Oh, D. J. Jung, D.S. Hwang, Yoon-Jong Song, Sung-Yung Lee, S.Y. Lee, In Soo Jung, June-Woo Lee, B.J. Koo, H.-J. Cho
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and str
Autor:
Chang-Jin Kang, Junekyun Park, Kwan-Heum Lee, Junha Lee, Jae-Hak Kim, Jin-Hyon Lee, Cheol Seong Hwang, Yongjik Park, R.J.G. Lee, K-C. Lee, D.H. Ko, Kangjung Kim, Byeong-hee Roh, J-H. Park, Byeung-Chul Kim
Publikováno v:
Proceedings of International Electron Devices Meeting.
In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi/sub x/ gate, Self-Aligned Contact (SAG),
Autor:
Yongjik Park, Kinam Kim
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
In this paper, the key technologies for future DRAM cells are investigated based on the COB stack cell for DRAM technology generations from 0.15 /spl mu/m node to 70 nm node. The issues and directions for 6 key technology areas are suggested for each