Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Yongchan Ban"'
Autor:
Hosoon Shin, Yongchan Ban, Jaebok Kil, Heecheol Hwang, Kyoungin Cho, Sangmin Sim, Bonghyun Lee, Insub Shin, Heeyeon Kim, Chaeyoung Jang
Publikováno v:
DTCO and Computational Patterning II.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::688045b03211b35ac5dc3266079d8a99
https://doi.org/10.1117/12.2658070
https://doi.org/10.1117/12.2658070
Autor:
Yongchan Ban
Publikováno v:
Journal of Nanoscience and Nanotechnology. 16:4684-4691
The An AC current induced electro-migration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower and suffer fr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a70a3436043e43fcea33b8b21fb5aef8
https://doi.org/10.1166/jnn.2016.12253
https://doi.org/10.1166/jnn.2016.12253
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
This paper presents improvements in performance, power, and area (PPA) obtained by optimizing the gear ratio (GR) between the Gate and vertical metal layer pitches in standard cells in sub-10nm node CMOS SoC designs. Changing the GR from 1:1 to 3:2 l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d6eb49a564c7fbd2fdf0501d0f488d0
https://doi.org/10.1109/vlsit.2018.8510670
https://doi.org/10.1109/vlsit.2018.8510670
IR-drop analysis for validating power grids and standard cell architectures in sub-10nm node designs
Publikováno v:
SPIE Proceedings.
Since chip performance and power are highly dependent on the operating voltage, the robust power distribution network (PDN) is of utmost importance in designs to provide with the reliable voltage without voltage (IR)-drop. However, rapid increase of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::956b55ac2cbc7aeb5d13b2d73477625e
https://doi.org/10.1117/12.2258340
https://doi.org/10.1117/12.2258340
Publikováno v:
SPIE Proceedings.
Traditional RC extraction flows mostly consider interconnect thickness variations caused by etch and CMP processes in a way of rule-based approach where a form of tables or polynomials is used. While such rulebased approaches are easily incorporated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d28347671555860685751e3fd4e20b9e
https://doi.org/10.1117/12.2219118
https://doi.org/10.1117/12.2219118
Autor:
Yongchan Ban, David Z. Pan
Publikováno v:
IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 1:150-159
Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithograp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5112055f7e3703ae71eb06be3b97da8
https://doi.org/10.1109/jetcas.2011.2159286
https://doi.org/10.1109/jetcas.2011.2159286
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:1006-1016
In this paper, we present an efficient lithography aware detailed (ELIAD) router to enhance silicon image after optical proximity correction (OPC) in a correct-by-construction manner. We first quantitatively show that a pre-OPC litho-metric is highly
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91876fe19ff2bf539d086ab2d58588e3
https://doi.org/10.1109/tcad.2009.2018876
https://doi.org/10.1109/tcad.2009.2018876
Autor:
Yongchan Ban
Publikováno v:
2015 International SoC Design Conference (ISOCC).
As the device dimension increases and chip sizes shrink, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. Thus, we need to ensure not only conventional design cl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0f8f9fb661c27cfaee4b31f46be7936
https://doi.org/10.1109/isocc.2015.7401655
https://doi.org/10.1109/isocc.2015.7401655
Publikováno v:
2015 International SoC Design Conference (ISOCC).
In this paper we have proposed a way of a model-based CMP proximity correction in sub-28nm SoC (system-on-a-chip) designs. Just like OPC (optical proximity correction) process against lithography variations, the proposed approach can be added at the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22daa49c8090fbdb05f26a7f6fc02f4b
https://doi.org/10.1109/isocc.2015.7401685
https://doi.org/10.1109/isocc.2015.7401685
Publikováno v:
ACM Great Lakes Symposium on VLSI
As minimum feature size and pitch spacing further decrease in advanced technology nodes, many new design constraints and challenges are introduced, such as regularity, middle of line (MOL) structures, and pin-access challenges. In this work, we propo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e93cd2800291d931edb58734036b3fb
https://doi.org/10.1145/2742060.2742084
https://doi.org/10.1145/2742060.2742084