Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Yong-sheng Yin"'
Publikováno v:
Chinese Journal of Liquid Crystal and Displays. 36:529-537
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ec79d2a71aeb33a5fb64ceaaae72ad3
https://doi.org/10.37188/cjlcd.2020-0299
https://doi.org/10.37188/cjlcd.2020-0299
Publikováno v:
Applied Mechanics and Materials. :3797-3801
A second-order single bit Sigma - Delta modulator which can be applied to pressure sensor is designed in this paper.The modulator uses switched-capacitor circuit,and the operational amplifier adopts a differential folded-cascode structure with PMOS t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e6148bae3a72d061d045b40f9e1c565
https://doi.org/10.4028/www.scientific.net/amm.644-650.3797
https://doi.org/10.4028/www.scientific.net/amm.644-650.3797
Publikováno v:
Advanced Materials Research. 748:847-852
A high performance sample-and-hold (S/H) circuit with input common mode feedback (ICMFB) is presented. The ICMFB is used to ensure that the input common mode voltage for the sample-and-hold amplifier (SHA) is maintained at a known value during the ho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ab0f8f6639df398f83340f47ed4e060
https://doi.org/10.4028/www.scientific.net/amr.748.847
https://doi.org/10.4028/www.scientific.net/amr.748.847
Publikováno v:
Advanced Materials Research. 748:853-858
Based on the latch and comparison theory, a high-speed high-resolution latched comparator is designed in this paper by using a standard 0.18μm/1.8V CMOS process. With the sampling frequency of 400MHz, the Cadence Spectre simulation results show that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b20d471d6f9b411c2c5a7aaed00c3beb
https://doi.org/10.4028/www.scientific.net/amr.748.853
https://doi.org/10.4028/www.scientific.net/amr.748.853
Publikováno v:
Advanced Materials Research. 748:868-873
An improved DWA method for 14-bit 5+4+5 segmented current-steering digital-to-analog converters is proposed. Through to SFDR and dynamic performance of compromise consideration, this method uses two barrel shifters to control the starting position of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::037e11ca9cc99da379651563f473d7f4
https://doi.org/10.4028/www.scientific.net/amr.748.868
https://doi.org/10.4028/www.scientific.net/amr.748.868
Publikováno v:
Journal of Electronics (China). 23:157-160
Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Comb
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9228323f7653814e34dfa885361b73b0
https://doi.org/10.1007/s11767-005-0026-9
https://doi.org/10.1007/s11767-005-0026-9
Publikováno v:
2012 5th International Congress on Image and Signal Processing.
The convergence speed is an important indicator of the digital background calibration technique for pipelined ADC. A Split-ADC architecture is used to calibrate the error resulting from capacitor mismatches and finite opamp dc gain in this work. Two
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b8327d24d2bd1c87ff402abe03d6e338
https://doi.org/10.1109/cisp.2012.6469847
https://doi.org/10.1109/cisp.2012.6469847
Publikováno v:
Communications in Computer and Information Science ISBN: 9783642181337
A low-jitter clock duty cycle corrector circuit applied in high performance ADC is presented in the paper, such circuits can change low accuracy input signals with different frequencies into 50% pulse width clock. The result have show that the circui
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::823327636fee9b8e588711c89fa59e31
https://doi.org/10.1007/978-3-642-18134-4_33
https://doi.org/10.1007/978-3-642-18134-4_33
Publikováno v:
2009 IEEE 8th International Conference on ASIC.
A mixed-signal calibration architecture and algorithm based upon 14bits 1.5b/s pipeline A/D converter is proposed1. The mixed-signal calibration algorithm consists of analog domain calibration and digital domain calibration. The analog-domain calibra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9bf17c54365344789d9258303557acef
https://doi.org/10.1109/asicon.2009.5351477
https://doi.org/10.1109/asicon.2009.5351477
Publikováno v:
APCCAS
A multi-pipeline dynamically reconfigurable system (MPRS) with coarse-grained processing elements is described in this paper. A systematic mapping method implemented by analyzing a dependence graph with reconfigurable variables (DGRV) based on an MPR
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2ba4febdf9c742b0520b4f38b8c45f4
https://doi.org/10.1109/apccas.2008.4745954
https://doi.org/10.1109/apccas.2008.4745954