Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Yong-Jhen Jiangn"'
Autor:
Yong-Jhen Jiangn, 江永鎮
99
The thesis describes the RF transceiver front-end chip design for DSRC (Dedicated Short Range Communications) applications, and two RF front-end chips are designed by the CMOS 0.18 μm process. For mobile wireless communications and low power
The thesis describes the RF transceiver front-end chip design for DSRC (Dedicated Short Range Communications) applications, and two RF front-end chips are designed by the CMOS 0.18 μm process. For mobile wireless communications and low power
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/5dmq33
Publikováno v:
International Symposium on Microelectronics. 2013:000820-000824
An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e5a781bffc05980e77c11699f24f8d24
https://doi.org/10.4071/isom-2013-thp21
https://doi.org/10.4071/isom-2013-thp21
Fractional-N Frequency Synthesizer and RF Receiver Front-End for Wireless Communications Application
Publikováno v:
International Conference on Software Intelligence Technologies and Applications & International Conference on Frontiers of Internet of Things 2014.
This paper presents a 0.18 μm CMOS low-power fractional-N frequency synthesizer with a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur and RF receiver front-end applying wireless communications systems is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce55a8d5ff7db4bba9526d122ce01bf6
https://doi.org/10.1049/cp.2014.1559
https://doi.org/10.1049/cp.2014.1559
Publikováno v:
Lecture Notes in Electrical Engineering ISBN: 9783319017655
A 5.8-GHz transceiver front-end applied in dedicated short-range communication (DSRC) systems which is developed in public traffic transportation to improve the safety is fabricated on a chip using TSMC 0.18-μm CMOS process. The proposed prototype i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2512170d49fab0102c11a7fc5ff452e
https://doi.org/10.1007/978-3-319-01766-2_118
https://doi.org/10.1007/978-3-319-01766-2_118
Publikováno v:
2011 International Symposium on VLSI Design, Automation & Test (VLSI-DAT); 2011, p1-4, 4p