Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Yong Jyun Hu"'
Autor:
Yong Jyun Hu, Wei Hwang, Paul Sen Kan, Ming-Hsien Tu, Ching-Te Chuang, Chen Chien Hen, Li Wei Chu, Yang Hao I, Shyh-Jye Jou, Nan Chun Lien
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:3416-3425
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6831aec55e7eb966d6c5c6aa1f0bf99d
https://doi.org/10.1109/tcsi.2014.2336531
https://doi.org/10.1109/tcsi.2014.2336531
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:1843-1847
This paper presents a march-like testTAC-P to cover comparison faults of ternary content addressable memories (TCAMs) with asymmetric cells. The TAC-P only requires 4N Write operations and (3N+2B) Compare operations for an N ×B -bit TCAM with Hit an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::099e099dbf8dd3dbc29ebdfa17986559
https://doi.org/10.1109/tcad.2010.2072710
https://doi.org/10.1109/tcad.2010.2072710
Autor:
Paul Sen Kan, Zhi Hao Chang, Ching-Te Chuang, Yu Hsuan Chen, Yung Shin Kao, Kuen Di Lee, Ming-Hsien Tu, Shyh-Jye Jou, Chao Kuei Chung, Huan Shun Huang, Yong Jyun Hu, Chien-Yu Lu
Publikováno v:
SoCC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd6edd8594ecc2dcd14d1afb27a72f08
https://doi.org/10.1109/socc.2014.6948972
https://doi.org/10.1109/socc.2014.6948972
Autor:
Chi-Shin Chang, Shyh-Jye Jou, Cheng-Yo Cheng, Nan-Chun Lien, Hao-I Yang, Wei-Chiang Shih, Paul-Sen Kan, Chien-Hen Chen, Wei-Nan Liao, Yi-Wei Lin, Jian-Hao Wang, Ming-Hsien Tu, Ching-Te Chuang, Kuen-Di Lee, Yong-Jyun Hu, Wei Hwang, Wei-Chang Wang, Chia-Cheng Chen, Huan-Shun Huang
Publikováno v:
ISCAS
We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Wr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd08d04ceaf2c5ba11e243a1a6b088e9
https://doi.org/10.1109/iscas.2013.6572134
https://doi.org/10.1109/iscas.2013.6572134
Autor:
Yong-Jyun Hu, 胡詠鈞
98
Three-dimensional (3-D) integrated chip (IC) design technology is now widely acknowledged as one of the future chip design technologies. A 3-D IC has many benefits over a conventional 2-D IC, such as small form factor, high functionality, hig
Three-dimensional (3-D) integrated chip (IC) design technology is now widely acknowledged as one of the future chip design technologies. A 3-D IC has many benefits over a conventional 2-D IC, such as small form factor, high functionality, hig
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/36278653279232408150
Publikováno v:
2009 IEEE International Workshop on Memory Technology, Design, and Testing.
Three-dimensional (3-D) integration is an emerging integrated circuit technology. Semiconductor memory is very suitable to be realized using 3-D technology due to its regularity. Different from random access memories (RAMs), a content addressable mem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce4b78b87652378255c9485d6ad37bca
https://doi.org/10.1109/mtdt.2009.20
https://doi.org/10.1109/mtdt.2009.20
Publikováno v:
VTS
Ternary content addressable memory (TCAM) is a key component in various applications for its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b34f186ef205f273a0d770ef4d5ce23
https://doi.org/10.1109/vts.2009.18
https://doi.org/10.1109/vts.2009.18
Publikováno v:
2009 27th IEEE VLSI Test Symposium; 2009, p15-20, 6p