Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Yong Cheol Peter Cho"'
Autor:
Jaehoon Chung, HyunMi Kim, Kyoungseon Shin, Chun-Gi Lyuh, Yong Cheol Peter Cho, Jinho Han, Youngsu Kwon, Young-Ho Gong, Sung Woo Chung
Publikováno v:
ETRI Journal, Vol 44, Iss 5, Pp 849-858 (2022)
Dynamic voltage frequency scaling (DVFS) has been widely adopted for runtime power management of various processing units. In the case of neural processing units (NPUs), power management of neural network applications is required to adjust the freque
Externí odkaz:
https://doaj.org/article/7019db6b66c447488c26803a9450cb76
Autor:
Yong Cheol Peter Cho, Jaehoon Chung, Jeongmin Yang, Chun‐Gi Lyuh, HyunMi Kim, Chan Kim, Je‐seok Ham, Minseok Choi, Kyoungseon Shin, Jinho Han, Youngsu Kwon
Publikováno v:
ETRI Journal, Vol 42, Iss 4, Pp 491-504 (2020)
We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteri
Externí odkaz:
https://doaj.org/article/b38d7df90356434ebdad7b6280b1415f
Autor:
Won Jeon, Yong Cheol Peter Cho, Hyun Mi Kim, Hyeji Kim, Jaehoon Chung, Juyeob Kim, Miyoung Lee, Chun-Gi Lyuh, Jinho Han, Youngsu Kwon
Publikováno v:
2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS).
Autor:
Hyun-Mi Kim, Jinho Han, Minseok Choi, Je-Seok Ham, Chan Kim, Kyoung-Seon Shin, Jeongmin Yang, Young-Su Kwon, Yong Cheol Peter Cho, Chun-Gi Lyuh, Jaehoon Chung
Publikováno v:
ETRI Journal, Vol 42, Iss 4, Pp 491-504 (2020)
We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteri
Autor:
Kyoung-Seon Shin, Chun-Gi Lyuh, Jeongmin Yang, Minseok Choi, Yong Cheol Peter Cho, Hyun-Mi Kim, Chan Kim, Je-Seok Ham, Hyeji Kim, Young-Su Kwon, Jinho Han, Jaehoon Chung
Publikováno v:
ISCAS
In this demonstration, we present AB9 SoC system, a single-chip solution for AI application. It provides the reconfigurable and programmable architecture to support the general computations for a variety of neural networks. The AB9 SoC is implemented
Autor:
Ju-Yeob Kim, Yong Cheol Peter Cho, Young-Su Kwon, Jinho Han, Jinkyu Kim, Je-Seok Ham, Chun-Gi Lyuh
Publikováno v:
HPC Asia
HPL(High Performance Linpack) is the standard benchmark used to evaluate supercomputers (high-performance computing systems) around the world. HPL solves a linear system of equations, Ax=b, through a series of mathematical processes such as 2D Block-
Autor:
Kyoung-Seon Shin, Yong Cheol Peter Cho, Hyun-Mi Kim, Jinho Han, Insan Jeon, Jeongmin Yang, Young-Su Kwon, Minseok Choi, Jaehoon Chung, Chan Kim, Chun-Gi Lyuh
Publikováno v:
ISOCC
AI processors are extending the application area into mobile and edge devices. The requirement of low power consumption which has been an essential factor in designing processors is now becoming the most critical factor for mobile AI processors to be
Autor:
Hyun-Mi Kim, Kyoung Seon Shin, Young-Su Kwon, Chan Kim, Minseok Choi, Yong Cheol Peter Cho, Jeongmin Yang, Jinho Han, In San Jeon, Chun-Gi Lyuh, Jaehoon Chung
Publikováno v:
ICCE-Berlin
An implementation of Yolo-v2 image recognition and other testbenches for a deep learning accelerator is presented. This chip is the initial version of our on-going effort for a higher performance accelerator development. The accelerator is based on a
Autor:
Kyoung-Seon Shin, Jeongmin Yang, Chun-Gi Lyuh, Jaehoon Chung, Jinho Han, Young-Su Kwon, Minseok Choi, Yong Cheol Peter Cho, Hyun-Mi Kim, Chan Kim
Publikováno v:
AICAS
State-of-the-art neural network accelerators consist of arithmetic engines organized in a mesh structure datapath surrounded by memory blocks that provide neural data to the datapath. While server-based accelerators coupled with server-class processo
Publikováno v:
A-SSCC
We present a processing platform that implements DMR with separate clock and power sources to prevent dependent failures working with a reconfigurable cache that includes BIST with self-recovering function to detect transient faults and error predict