Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Yogendra Sao"'
Autor:
Yogendra Sao, Sk. Subidh Ali
Publikováno v:
IEEE Transactions on Information Forensics and Security. 18:2842-2855
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb94a10ac5ba964ccaeefabaf968c03e
https://doi.org/10.1109/tifs.2023.3265815
https://doi.org/10.1109/tifs.2023.3265815
Publikováno v:
2022 IEEE European Test Symposium (ETS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00009b79af45c54fe0d8341b2f20673b
https://doi.org/10.1109/ets54262.2022.9810460
https://doi.org/10.1109/ets54262.2022.9810460
Autor:
Yogendra Sao, Sk Subidh Ali
Publikováno v:
2021 IEEE 39th International Conference on Computer Design (ICCD).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::657b202496e97e7a31f2bc83f369cd91
https://doi.org/10.1109/iccd53106.2021.00096
https://doi.org/10.1109/iccd53106.2021.00096
Publikováno v:
ETS
Scan based DfT is the de facto standard for testing the functional and structural correctness of chips. It provides high observability and controllability of internal latches leading to enhanced fault coverage, but can also induce vulnerability in cr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e532df12024f2bb0f2cbc52d5aa103d
https://doi.org/10.1109/ets50041.2021.9465427
https://doi.org/10.1109/ets50041.2021.9465427
Publikováno v:
AsianHOST
Scan-based Design for Testability (DfT) provides high fault coverage, observability, and testability of internal nodes of the chip. It can serve as a medium for the attacker to launch a side-channel attack and thus reveal the secret key embedded in t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49d144fb0c7b511df794396c930bdf44
https://doi.org/10.1109/asianhost51057.2020.9358266
https://doi.org/10.1109/asianhost51057.2020.9358266
Publikováno v:
Microelectronics Reliability. 123:114216
Scan based DfT is indispensable for IC testing in the semiconductor chip industry to ensure correctness of chip, both functionally and structurally. Since a higher degree of fault coverage is essential, cryptographic ICs rely on it as a standard tech
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f7ad362136c0a69103e711d79fa9b0e3
https://doi.org/10.1016/j.microrel.2021.114216
https://doi.org/10.1016/j.microrel.2021.114216