Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Yinkun Huang"'
Publikováno v:
Jixie chuandong, Vol 45, Pp 85-92 (2021)
The contact characteristics of a nutation drive with double circular-arc spiral bevel gears are extremely sensitive to installation errors. To reveal the effects of installation errors on contact characteristics，the tooth surface contact analysis o
Externí odkaz:
https://doaj.org/article/c77c5066b5ad4daf8824bdaca848ac34
Publikováno v:
Mechanism and Machine Theory. 176:105001
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86e4065f34af698d00b54002e0ea4f68
https://doi.org/10.1016/j.mechmachtheory.2022.105001
https://doi.org/10.1016/j.mechmachtheory.2022.105001
Publikováno v:
ISCAS
In this paper, a time-interleaved 10GS/s 8bit ADC fabricated in 0.18μm SiGe BiCMOS technology has been demonstrated. The proposed 4×4 input multiplexer allows the ADC to support 1/2/4-channel sampling modes with no compromised isolation and input b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b0b33660faefb24a084b0422dfa8925
https://doi.org/10.1109/iscas.2019.8702485
https://doi.org/10.1109/iscas.2019.8702485
Autor:
Nanxun Wu, Danyu Wu, Xuqiang Zheng, Jian Luan, Xinyu Liu, Xuan Guo, Jin Wu, Hanbo Jia, Yinkun Huang, Lei Zhou
Publikováno v:
Electronics, Vol 9, Iss 910, p 910 (2020)
Electronics
Volume 9
Issue 6
Electronics
Volume 9
Issue 6
This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective samplin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e6708cb90b3e667af17bd984dd736d11
https://doi.org/10.3390/electronics9060910
https://doi.org/10.3390/electronics9060910
Autor:
Jianwen Li, Jian Luan, Xuan Guo, Xinyu Liu, Danyu Wu, Jin Wu, Hanbo Jia, Xuqiang Zheng, Lei Zhou, Nanxun Wu, Yinkun Huang
Publikováno v:
Electronics, Vol 9, Iss 2, p 375 (2020)
Electronics
Volume 9
Issue 2
Electronics
Volume 9
Issue 2
A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c666ebdb01d9cf618dc03b45615421b9
https://doi.org/10.3390/electronics9020375
https://doi.org/10.3390/electronics9020375
Autor:
Danyu Wu, Xuan Guo, Hanbo Jia, Jianwen Li, Lei Zhou, Yinkun Huang, Xuqiang Zheng, Jin Wu, Jian Luan, Nanxun Wu, Xinyu Liu
Publikováno v:
Electronics
Volume 8
Issue 12
Volume 8
Issue 12
This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::29cca657543f4fb55ac8beb0d2cfcc99
https://doi.org/10.3390/electronics8121551
https://doi.org/10.3390/electronics8121551
Publikováno v:
Science China Information Sciences. 60
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27143f5d93ced25f00c898ac66bbfdf6
https://doi.org/10.1007/s11432-016-0711-y
https://doi.org/10.1007/s11432-016-0711-y
Publikováno v:
Analog Integrated Circuits and Signal Processing. 81:341-348
This article presents a wideband calibration-free 8-bit analog-to-digital converter (ADC) with low latency. The ADC employs a two-stage cascaded folding and interpolating architecture. A high-linearity and wideband track-and-hold amplifier combined w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8345760c26b8721362a77c609b477ce
https://doi.org/10.1007/s10470-014-0359-0
https://doi.org/10.1007/s10470-014-0359-0
Autor:
Huasen Liu, Xuqiang Zheng, Xuan Guo, Dong Wang, Jian Luan, Lei Zhou, Yinkun Huang, Xinyu Liu, Danyu Wu, Jin Wu
Publikováno v:
IEICE Electronics Express. 16:20181079-20181079
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ffbc0dcaae70521147c4534de0ac800
https://doi.org/10.1587/elex.16.20181079
https://doi.org/10.1587/elex.16.20181079
Publikováno v:
2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM).
In this paper, a time-interleaved 30GS/s 6bit ADC fabricated in 0.18µm SiGe BiCMOS technology has been demonstrated. A bandwidth boosting technique and packaging solution has been proposed which enables the ADC to achieve input bandwidth over 18GHz.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea8f3760bceaca1da0abd9a082e47157
https://doi.org/10.1109/bctm.2016.7738968
https://doi.org/10.1109/bctm.2016.7738968