Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Ying-Chih Lee"'
Autor:
Ying-Chih Lee, 李盈志
94
The research studies efficiency of wireless communication industry in Taiwan, and it uses different DEA models to analyze and compare with input and output performances in different years from examined companies. In order to assess the perfor
The research studies efficiency of wireless communication industry in Taiwan, and it uses different DEA models to analyze and compare with input and output performances in different years from examined companies. In order to assess the perfor
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/94837328066071427468
Publikováno v:
2021 International Conference on Electronics Packaging (ICEP).
Asymmetric warping is an annoying phenomenon impacting the packaging reliability and must be reduced by modifying design and process parameters through proper prediction. Traditionally, highly meshed finite element simulations are usually used. Howev
Autor:
KarenYU Chen, Eddie Tsai, CP Hung, Tang-Yuan Chen, Lung Tsai, PeterBS Chen, Meng-Kai Shih, Ian Hu, Eatice Chen, Ying-Chih Lee, Ryan Chen, David Tarng
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
In recent years, Fan-Out (FO) packages have become widely used in handheld, mobile consumer and internet of things (IoT) devices. FO packaging enables a greater I/O density as well as multiple components in the same package. Several types of FO packa
Autor:
Hsiao-Yen Lee, Chin-Cheng Kuo, Chung-Ting Wang, Chih-Pin Hung, Ming-Hung Chen, Ying-Chih Lee, Hsin-Lu Tarng
Publikováno v:
2017 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS).
The through-silicon-via (TSV) technology is one of the most effective approaches to fulfill the form factor, profile, performance, and 3D interconnect demand of next generation handheld and wearable electronics. This paper introduces two structures o
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
Fan-Out (FO) chip on substrate is one of the fan-out solution for package integration. This solution brings the short interconnection between die to die for excellent electrical performance. Fan-Out chip on substrate device provides excellent electri
Publikováno v:
2017 International Conference on Electronics Packaging (ICEP).
Wafer-level chip-scale package (WLCSP) with solder joint as interconnection process was used to enable, thinner, low cost and fine-pitch for mobile type of information and communication device that assembly into SiP module. However, the lower solder
Publikováno v:
2017 International Conference on Electronics Packaging (ICEP).
Smaller form factor, thermal/electrical efficiency and low-cost manufacturing are characteristics of the wafer level chip scale package (WLCSP) which had been widely used by market demand especially in handheld and portable applications in past sever
Publikováno v:
2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Wafer Level Chip Scale Package (WLCSP) has been widely used in MEMS and SiP packages; application of mobile and consuming products. It advantages in lightweight, reducing manufacturing cost, low I/O density and high performance because the bumps dire
Autor:
Dao-Long Chen, Hsiao-Yen Lee, Hung-Hsiang Cheng, Ying-Chih Lee, Chin-Cheng Kuo, Chen-Chao Wang, Ying-Te Ou, Meng-Kai Shih, Ping-Feng Yang
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
The through-silicon-via (TSV) technology is one of the most effective approaches to fulfill the form factor, profile, performance, and 3D interconnect demand of next generation handheld and wearable electronics. The TSV technology has been developed