Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Yigi Kwon"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:961-971
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::078fda8fb6a491794e7d2b573a251d6b
https://doi.org/10.1109/jssc.2023.3235521
https://doi.org/10.1109/jssc.2023.3235521
Publikováno v:
IEEE Solid-State Circuits Letters. 4:166-169
This letter presents a two-stage dynamic amplifier that achieves the high dc gain and PVT robustness of the residue amplifier in a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The proposed dynamic amplifier ope
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e572305b35288b70e37725b54d4d81da
https://doi.org/10.1109/lssc.2021.3114318
https://doi.org/10.1109/lssc.2021.3114318
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee408177d511538e5b4d6e378e177e4e
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830300
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830300
Publikováno v:
ISCAS
This paper proposes a pipeline ADC consisting of a first stage SAR ADC and a second stage Flash ADC. This ADC has a 10-bit resolution at 0.9 V power supply voltage and operates at 400 MS/s. The first stage SAR ADC is 6bit resolution, operates in an a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e155f3e8daf5bfda7eba526b4e9edfb
https://doi.org/10.1109/iscas51556.2021.9401263
https://doi.org/10.1109/iscas51556.2021.9401263