Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Yew Keong Chong"'
Autor:
Andy Wangkun Chen, Mudit Bhargava, Tan Peixuan, Yulin Shi, Mark P. McCartney, Yew Keong Chong, Cagla Cakir, Sriram Thyagarajan
Publikováno v:
VLSI Circuits
We present a high-performance 6T SRAM architecture equipped with low-power features of late cancel, left-right enable, input-gating, and power-gating. Measurements show that these SRAMs can support CPUs running at 4GHz while offering dynamic power sa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b3edab1f64137c637378b62dc048f23
https://doi.org/10.23919/vlsic.2019.8778108
https://doi.org/10.23919/vlsic.2019.8778108
Autor:
Abhishek Baradia, Andy Wangkun Chen, Mudit Bhargava, Bikas Maiti, Jacek Wiatrowski, Vincent Schuppe, Sriram Thyagarajan, Gus Yeung, Yew Keong Chong, Hsin-Yu Chen, Gerald Gouya, Sanjay Mangal, Martin Kinkade
Publikováno v:
VLSIC
Measured results of V MIN from 20nm SRAM arrays with read and write assist techniques are presented for multiple flavors of bitcell. A novel assist technique is presented, that provides both read and write assist by controlling only the voltage of wo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6687cecbc4db99b6d22e0a792f8944c
https://doi.org/10.1109/vlsic.2014.6858412
https://doi.org/10.1109/vlsic.2014.6858412
Autor:
Chris Hawkins, Pranay Prabhat, Paul Darren Hoxey, Gus Yeung, Yew Keong Chong, Dermot O'Driscoll
Publikováno v:
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.
Dynamic power is a keenly analysed design parameter in SRAM memory design especially in low power battery operated systems. A simple way to reduce dynamic power (and leakage power) is to lower the operating voltage to the minimum possible for a given
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7da1eaf65ea688eaed84edf98a0bde32
https://doi.org/10.1109/vdat.2011.5783619
https://doi.org/10.1109/vdat.2011.5783619