Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Yesh Kolla"'
Autor:
Jihoon Jeong, Francois Ibrahim Atallah, Keith Bowman, J. Todd Bridges, Daniel Yingling, Brad Appel, Sarthak Raina, David W. Hansquine, Hoan Huu Nguyen, Yesh Kolla
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:8-17
A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage $({\rm V}_{\rm DD})$ droops. The ACD integrates a tuna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4a5bb073b6ab4cb4e1d338ceb6cf847
https://doi.org/10.1109/jssc.2015.2473655
https://doi.org/10.1109/jssc.2015.2473655
Publikováno v:
Analog Integrated Circuits and Signal Processing. 83:295-309
A fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators developed for voltage regulation in portable devices and fabricated in a 28 nm CMOS process is described. Each LDO employs adaptive bias for fast and power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62a7b543be246e5d20cd6ef1055f015e
https://doi.org/10.1007/s10470-015-0526-y
https://doi.org/10.1007/s10470-015-0526-y
Autor:
Hoan Nguyen, Keith Bowman, Jihoon Jeong, Daniel Yingling, Yesh Kolla, Francois Ibrahim Atallah, Brad Appel, Todd Bridges, David W. Hansquine, Sarthak Raina
Publikováno v:
ISSCC
System-on-chip (SoC) processor cores experience high-frequency supply voltage (V DD ) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e101fc6371f0e48adf1671fbb098f34
https://doi.org/10.1109/isscc.2015.7062971
https://doi.org/10.1109/isscc.2015.7062971
Publikováno v:
ISSCC
The high-performance needs of mobile products has motivated CPU designers to increase processing performance while decreasing power consumption. A dual-issue out-of-order superscalar ARMv7-architecture CPU uses the technique of register-renaming to r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9f321b949fed7c9f44372108c6dca37
https://doi.org/10.1109/isscc.2010.5433924
https://doi.org/10.1109/isscc.2010.5433924