Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Yeongon Cho"'
Publikováno v:
IEEE Access, Vol 11, Pp 133199-133214 (2023)
With the rapid growth in memory demands, the slowdown of DRAM scaling, and the DRAM price fluctuations, DRAM has become one of the critical resources in cloud computing systems and datacenters. The compressed memory swap (CMS) is a promising techniqu
Externí odkaz:
https://doaj.org/article/64af783f353f44d881ad9f347e292d96
Autor:
Jin Hyun Kim, Shin-Haeng Kang, Sukhan Lee, Hyeonsu Kim, Yuhwan Ro, Seungwon Lee, David Wang, Jihyun Choi, Jinin So, YeonGon Cho, JoonHo Song, Jeonghyeon Cho, Kyomin Sohn, Nam Sung Kim
Publikováno v:
IEEE Micro. 42:20-30
Autor:
Hsien-Hsin S. Lee, Il-Kwon Yun, Jin Jung, Jong Geon Lee, Jinin So, Shin-haeng Kang, Liu Ke, Joon-Ho Song, Xuan Zhang, Han Songyi, Kyomin Sohn, Jin-Hyun Kim, Sukhan Lee, Jeonghyeon Cho, Kyung-Soo Kim, Yeongon Cho, Hyunsun Park, Yongsuk Kwon, Sung Joo Park, Nam Sung Kim
Publikováno v:
IEEE Micro. 42:116-127
Near-memory processing (NMP) is a prospective paradigm enabling memory-centric computing. By moving the compute capability next to the main memory (DRAM modules), it can fundamentally address the CPU-memory bandwidth bottleneck and thus effectively i
Autor:
Bengseng Phuah, Hyun-Sung Shin, Jinin So, Shin-haeng Kang, Kyomin Sohn, Wang David T, Kwang-Il Park, Hyeon-Su Kim, Jihyun Choi, Joon-Ho Song, Jeonghyeon Cho, Jin-Hyun Kim, Yu-Hwan Ro, Woong-jae Song, Sukhan Lee, Seung-Won Lee, Young-Soo Sohn, Yeongon Cho, Jang-Seok Choi, Nam Sung Kim
Publikováno v:
HCS
Using PIM to overcome memory bottleneck • Although various bandwidth increase methods have been proposed, it is physically impossible to achieve a breakthrough increase. - Limited by # of PCB wires, # of CPU ball, and thermal constraints • PIM ha
Publikováno v:
Electronics Letters, Vol 52, Iss 9, Pp 692-694 (2016)
An inverted bit-line sense amplifier (BLSA) equipped with offset compensation capability for low-power DRAM applications is proposed. The sequential operation of the inverted BLSA allows us to eliminate the edge dummy array in an open bit-line struct
Publikováno v:
FPT
The latest biomedical applications require low energy consumption, high performance, and wide energy-performance scalability to adapt to various working environments. In this study, we present ULP-SRP, an energy-efficient reconfigurable processor for
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:1748-1761
There has been extensive research on mapping and scheduling tasks on a many-core SoC. However, none considers the optimization of communication types, which can significantly affect performance, energy consumption, and local memory usage of the SoC.
Publikováno v:
HPCA
Thread or warp scheduling in GPGPUs has been shown to have a significant impact on overall performance. Recently proposed warp schedulers have been based on a greedy warp scheduler where some warps are prioritized over other warps. However, a single
Publikováno v:
ICCE
Low-power processing of multimedia data is mandatory for the recent mobile devices. In this paper, we present coarse-grained reconfigurable processor for low-power audio processing. By utilizing perfect instruction cache and tightly-coupled scratchpa
Publikováno v:
ICCE
This paper presents an implementation of seeded region growing (SRG) algorithm on multi-core system to achieve real time constraint with high precision. The proposed implementation has dynamic load balancing feature inherently and shows a speedup of