Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Yeong-Taek Lee"'
Autor:
Hui-jung Kim, Hyun-Gi Kim, Young-Hyun Jun, Gyo-Young Jin, Donggun Park, Jin-Young Kim, Jae-Man Yoon, Sua Kim, Ki-whan Song, Jei-Hwan Yoo, Hyun-Chul Kang, Chang-Hyun Kim, Duk-ha Park, Hwan-Wook Park, Kang-Uk Kim, Yeong-Taek Lee, Woo-Seop Kim, Nam-Kyun Tak, Kyungseok Oh, Yong Chul Oh, Hyun-Woo Chung
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:880-888
A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3787a1b86ee135b11b8596eb33058671
https://doi.org/10.1109/jssc.2010.2040229
https://doi.org/10.1109/jssc.2010.2040229
Autor:
Hoosung Cho, Doo-gon Kim, Ki-Tae Park, Yeong-Taek Lee, Hansoo Kim, Soon-Moon Jung, Jae-Hoon Jang, Soonwook Hwang, Myounggon Kang, Youngwook Jeong, Yong-Il Seo, Chang-Hyun Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:208-216
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To su
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b32f938fde8d4137c27a41345287899c
https://doi.org/10.1109/jssc.2008.2006437
https://doi.org/10.1109/jssc.2008.2006437
Autor:
Doo-gon Kim, Yeong-Taek Lee, Myounggon Kang, Byung Yong Choi, Chang-Hyun Kim, Soonwook Hwang, Kinam Kim, Ki-Tae Park
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:919-928
A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64daaab960ff04c50753ef250abfc236
https://doi.org/10.1109/jssc.2008.917558
https://doi.org/10.1109/jssc.2008.917558
Autor:
Ki-Sung Kim, In-Gyu Baek, Kye-Hyun Kyung, Yeong-Taek Lee, Chi-Weon Yoon, Hyo-Jin Kwon, Yong-kyu Lee, Dae Seok Byeon, Young-Bae Kim, Hyun-Kook Park, Yong-Yeon Joo, Jeong-Hyuk Choi, Jeong-Dal Choi
Publikováno v:
2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS).
In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf2064c975921c97b272527e1cd14efa
https://doi.org/10.1109/nvmts.2014.7060837
https://doi.org/10.1109/nvmts.2014.7060837
Autor:
Jung-Dal Choi, Young-Ho Lim, Wook-Ghee Hwasung Han, Dong-Hwan Kim, Yeong-Taek Lee, Seung-jae Lee, Kang-Deog Suh, Sun-Mi Choi, Jin-Wook Lee, Eun-cheol Kim, Cho Tae-Hee, Jae-Duk Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1700-1706
A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level program cell (SLC) modes, is fabricated with a 0.15-/spl mu/m CMOS technology. Utilizing simultaneous operation of four
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04c0936c9c8b7d73c744f32f3821f789
https://doi.org/10.1109/4.962291
https://doi.org/10.1109/4.962291
Publikováno v:
IEEE Transactions on Electron Devices. 47:2326-2333
A quasi-two-dimensional (2-D) threshold voltage reduction model for buried channel pMOSFETs is derived. In order to account for the coexistence of isoand anisotype junctions in a buried channel structure, we have incorporated charge sharing effect in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3bdc0d0c0f246d72c2afcc4cc4a6ba17
https://doi.org/10.1109/16.887015
https://doi.org/10.1109/16.887015
Autor:
Jun-Ho Shin, Su-Jin Ahn, Yeong-Taek Lee, Han-Sung Joo, Jung Sunwoo, Jei-Hwan Yoo, Hoe-ju Chung, Yong-Jin Kwon, Jaehwan Kim, Beakhyoung Cho, Jae-Wook Lee, Chang-Soo Lee, Yong-Jun Lee, Mu-Hui Park, Gitae Jeong, Sang-Hoan Chang, Jin-Young Kim, Soehee Kim, Mingu Kang, Duckmin Kwon, Young-Hoon Oh, Kwang-Jin Lee, Qi Wang, Young-don Choi, Yoohwan Rho, Jae-Yun Lee, Ickhyun Song, Hideki Horii, Sooho Cha, Ki-Sung Kim
Publikováno v:
ISSCC
Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-N
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f5ac863917e36ad25b5701fc52bcd26
https://doi.org/10.1109/isscc.2012.6176872
https://doi.org/10.1109/isscc.2012.6176872
Autor:
Sung Hwan Kim, Jae-Wook Lee, Woo-Seop Kim, Hoon Jeong, Young-Tae Kim, Yong Chul Oh, Nam-Kyun Tak, Yeong-Taek Lee, Han Sung Joo, Ki-Whan Song, Ho Ju Song, Changhyun Kim, Sung In Hong, Kyungseok Oh, Yong Lack Choi
Publikováno v:
2008 IEEE International Electron Devices Meeting.
This paper presents a capacitor-less 1T DRAM cell transistor with high scalability and long retention time. It adopts gate to source/drain non-overlap structure to suppress junction leakage, which results in 80 ms retention time at 85degC with gate l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36ccf1921083ce0a987e926baedfb826
https://doi.org/10.1109/iedm.2008.4796818
https://doi.org/10.1109/iedm.2008.4796818
Autor:
Kitae Park, Myounggon Kang, Yeong-Taek Lee, Han-soo Kim, Hoosung Cho, Youngwook Jeong, Soonwook Hwang, Yong-ll Seo, Jae-Hoon Jang, Won-Seong Lee, Chang-Hyun Kim, Doo-gon Kim, Soon-Moon Jung
Publikováno v:
ISSCC
Recently, 3-dimensional (3D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance. We present a 3D double stacked 4Gb MLC NAND flash memory device with shared bitline structure,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2968e55b5c5d0e4823abfa1d8dd4231e
https://doi.org/10.1109/isscc.2008.4523281
https://doi.org/10.1109/isscc.2008.4523281
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high disc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c1b52eed98cb9753a617d284e1cf765
https://doi.org/10.1109/asscc.2007.4425767
https://doi.org/10.1109/asscc.2007.4425767