Zobrazeno 1 - 10
of 53
pro vyhledávání: '"Yeonbae Chung"'
Autor:
Yeonbae Chung, Sivasundar Manisankar
Publikováno v:
International Journal of Circuit Theory and Applications. 46:1416-1425
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7e6cedf3b173bcce8bdbb8b9879232e
https://doi.org/10.1002/cta.2496
https://doi.org/10.1002/cta.2496
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 16:781-792
This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6b809fd18eafad1fbefb80cd83beadd
https://doi.org/10.5573/jsts.2016.16.6.781
https://doi.org/10.5573/jsts.2016.16.6.781
Publikováno v:
Electronics
Volume 9
Issue 6
Electronics, Vol 9, Iss 928, p 928 (2020)
Volume 9
Issue 6
Electronics, Vol 9, Iss 928, p 928 (2020)
Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they eithe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d43268265242d7539e187af54f9098ab
https://doi.org/10.3390/electronics9060928
https://doi.org/10.3390/electronics9060928
Publikováno v:
2018 5th International Conference on Electrical and Electronic Engineering (ICEEE).
With scaling of CMOS technology, data stability of SRAM at ultra-low supply voltage has become a critical issue for wearable system applications. In this paper, we present an advanced 8T SRAM which can operate properly in subthreshold voltage regime.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ecf473bb6f88ab591f53c1e8a1be035
https://doi.org/10.1109/iceee2.2018.8391356
https://doi.org/10.1109/iceee2.2018.8391356
Publikováno v:
2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).
In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c858038670bc496a27c849f11957a84
https://doi.org/10.1109/edssc.2017.8126401
https://doi.org/10.1109/edssc.2017.8126401
Autor:
Yeonbae Chung, Weijie Cheng
Publikováno v:
IET Circuits, Devices & Systems. 8:107-117
The design and physical implementation of an embedded memory utilising bit-area efficient hybrid gain cell is presented. The memory cells in this work are composed of a high-threshold NMOS write transistor and a standard-threshold NMOS read transisto
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cb17adf2cdf700369c4e2bde1f36488
https://doi.org/10.1049/iet-cds.2013.0234
https://doi.org/10.1049/iet-cds.2013.0234
Autor:
Yeonbae Chung
Publikováno v:
International Journal of Electronics. 101:831-848
The stability and leakage power of SRAMs have become an important issue with scaling of CMOS technology. This article reports a novel 8-transistor (8T) SRAM cell improving the read and write stability of data storage elements and reducing the leakage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::064b3f23952d31e6b5829b4e3d60c4cf
https://doi.org/10.1080/00207217.2013.805355
https://doi.org/10.1080/00207217.2013.805355
Autor:
Yeonbae Chung, Jung-Chan Lee
Publikováno v:
International Journal of Electronics. 97:273-283
In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since char
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d7ff080601871f41913f7cd14bfe14e5
https://doi.org/10.1080/00207210903289367
https://doi.org/10.1080/00207210903289367
Autor:
Weijie Cheng, Yeonbae Chung
Publikováno v:
IEICE Electronics Express. 7:1145-1151
The design and physical implementation of a low-power SRAM with 4T CMOS latch bit-cell is presented. The memory cells in this work are composed of two cross-coupled inverters without any access transistors. They are accessed by totally novel read and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62290e9b9931603de6302305012dde42
https://doi.org/10.1587/elex.7.1145
https://doi.org/10.1587/elex.7.1145
Autor:
Yeonbae Chung, Seung Ho Song
Publikováno v:
Microelectronics Journal. 40:944-951
This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are intern
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05e3b5ffd3d3d029b4e4e49d04552fdd
https://doi.org/10.1016/j.mejo.2008.11.063
https://doi.org/10.1016/j.mejo.2008.11.063