Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Yeoh Andrew W"'
Autor:
Benjamin J. Orr, Nathan Jack, C. Auth, A. Schmitz, Tony Acosta, Steven S. Poon, Che-Yun Lin, Abdur Rahman, C. AnDyke, Rahim Kasim, K. Downes, G. McPherson, Sunny Chugh, Madhavan Atul, D. Nminibapiel, Adam Neale, K. Sethi, Seung Hwan Lee, S. Ramey, Tanmoy Pramanik, Michael L. Hattendorf, Emre Armagan, J. Palmer, Subhash M. Joshi, Ian R. Post, C. M. Pelto, P. Nayak, Yeoh Andrew W, G. Martin, Gerald S. Leatherman, H. Wu, N. Seifert, A. Lowrie, R. Grover, H. Mao
Publikováno v:
IRPS
We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76e7a8286d09b3f3bfcb1c27f6a51e61
https://doi.org/10.1109/irps45951.2020.9128345
https://doi.org/10.1109/irps45951.2020.9128345
Autor:
Kaizad Mistry, Simeon Realov, Yeoh Andrew W, Chin-Hsuan Chen, Ranjith Kumar, Ian R. Post, Ying Zhang, Tai-Hsuan Wu, Somashekar Bangalore Prakash, Madhavan Atul, Quan Shi, Xinning Wang, Peng Zheng, Gadigatla Srinivasa Chaitanya, Nabors Marni, Chris Portland Auth
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e47600e063f4c3676ee823f1726d2eed
https://doi.org/10.1109/iedm.2018.8614662
https://doi.org/10.1109/iedm.2018.8614662
Autor:
Yeoh Andrew W, W. Han, Manvi Sharma, J. Shin, I. Post, M. Tanniru, T. Mule, Madhavan Atul, Gerald S. Leatherman, Kevin J. Fischer, Y-H. Wu, M. Sprinkle, Prasun Sinha, S. Anand, J. Steigerwald, S. Nigam, V. Souw, C. Ganpule, M. Asoro, Haran Mohit K, K-S. Lee, C. Pelto, P. Yashar, S. Samarajeewa, M. Mori, A. Tripathi, S. Kirby, C. Auth, M. Aykol, H. Hiramatsu, K. Marla, H. Jeedigunta, V. Chikarmane, M. Buehler, Nicholas J. Kybert
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
This paper describes Intel's 10nm highperformance logic technology interconnect stack featuring 13 metal layers comprising two self-aligned quad patterned and four self-aligned double patterned layers. Quad patterned interconnect layers are introduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fa7cc3fb3c8d31dc8c2da50fdf17147
https://doi.org/10.1109/iitc.2018.8430489
https://doi.org/10.1109/iitc.2018.8430489
Autor:
Rahim Kasim, J. Palmer, A. Schmitz, I. Tsameret, F. Pan, C. Auth, Flavio Griggio, Yeoh Andrew W, Gerald S. Leatherman, Joseph M. Steigerwald, J. Hicks, J. Shin, A. Madhavan, N. Toledo
Publikováno v:
IRPS
This paper discusses the reliability of a new metallization scheme for 10nm back end of line (BEOL) local interconnect. Electromigration (EM) and time dependent dielectric breakdown (TDDB) on cobalt fill interconnects are investigated. Significant in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58d63251175c58f96eca878418f6167f
https://doi.org/10.1109/irps.2018.8353641
https://doi.org/10.1109/irps.2018.8353641
Autor:
Robert M. Bigwood, J. Neirynck, V. Chikarmane, Michael A. Childs, Yeoh Andrew W, J. Neulinger, Y. Neirynck, D. Becher, J. Choi, P. Plekhanov, P. Yashar, M. Weiss, B. McFadden, G. Malyavantham, S. Klopcic, F. Xia, Jun He, Y. Shusterman, Saurabh Agrawal, S. Williams, S. Daviess, T. Van, C. Ganpule, Ruth A. Brain, C. Pelto, P. Hentges, I. Jin, M. Buehler
Publikováno v:
2009 IEEE International Interconnect Technology Conference.
Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7426bfd607ab2178c02069a496293925
https://doi.org/10.1109/iitc.2009.5090400
https://doi.org/10.1109/iitc.2009.5090400
Autor:
S. Lodha, J. Seiple, T. Troeger, S. Pae, G. Ding, Tahir Ghani, I. Jin, L. Pipes, C.-H. Chang, Ruth A. Brain, Cory E. Weber, Jun He, Kevin Zhang, Paul A. Packan, Robert James, R. Heussner, Seung Hwan Lee, S. Klopcic, W. Han, Anand Portland Murthy, Michael A. Childs, K. Dev, J. Neirynck, Mark Y. Liu, J. Sebastian, B. McFadden, Oleg Golonzka, Swaminathan Sivakumar, V. Chikarmane, C. Pelto, H. Deshpande, Sanjay Natarajan, Mark Armstrong, M. Yang, L. Neiberg, Mark R. Brazier, B. Song, Yeoh Andrew W, C. Parker, C. Kenyon, M. Bost, K. Tone, Sell Bernhard
Publikováno v:
2008 IEEE International Electron Devices Meeting.
A 32 nm generation logic technology is described incorporating 2nd-generation high-k + metal-gate technology, 193 nm immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT hig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e61e7413da3a7648aaa6f2eabc4f37c
https://doi.org/10.1109/iedm.2008.4796777
https://doi.org/10.1109/iedm.2008.4796777
Autor:
P. Stover, Yeoh Andrew W, Zhiyong Wang, C. Pelto, M. Chang, Tzuen-Luh Huang, S. Balakrishnan, S. Agraharam, D. Chiang, P. Brandenburger, Guotao Wang, G. Leatherman
Publikováno v:
56th Electronic Components and Technology Conference 2006.
The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::add1f0031b077856ce31a06d56ee7efb
https://doi.org/10.1109/ectc.2006.1645872
https://doi.org/10.1109/ectc.2006.1645872
Autor:
Bruce Woolery, Swaminathan Sivakumar, C. Kenyon, Ramune Nagisetty, M. Bost, Cory E. Weber, P. Bai, Jack Hwang, T. Marieb, C. Auth, Kevin Zhang, Andrew Ott, Yeoh Andrew W, Sridhar Balakrishnan, D. Ingerly, C. Parker, J. Sebastian, Ruth A. Brain, Makarem A. Hussein, J. Neirynck, Anand Portland Murthy, Z. Ma, Seung Hwan Lee, Nick Lindert, Joseph M. Steigerwald, E. Lee, Mark Y. Liu, R. Shaheed, M. Bohr, R. Heussner, J. Jeong, V. Chikarmane, Sanjay Natarajan, R. James, S. Tyagi
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac646c890427393477aae9a64374b642
https://doi.org/10.1109/iedm.2004.1419253
https://doi.org/10.1109/iedm.2004.1419253