Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Yeng-Kaung Peng"'
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 13:286-292
In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 12:313-322
Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel len
Publikováno v:
1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop ASMC 97 Proceedings.
This project integrates flexible data collection module, relational database, manufacturing execution system (MES) interface, and a simulation system that employs statistical approach and advanced numerical processing methodology. Concept of process-
Publikováno v:
1997 2nd International Workshop on Statistical Metrology.
The ever-growing demand to increase speed by shrinking device geometries has driven manufacturers to take more drastic measures in defect reduction. The installation of the state-of-the-art air filtration systems has shifted the focus from human-caus
Publikováno v:
Scopus-Elsevier
In-situ Particle Monitors (ISPM) have been adopted in the industry for optimizing cleaning cycles and detecting equipment abnormalities. However, in advanced manufacturing environments where the equipment is well maintained and where yield-dominating
Autor:
Ly Nguyen, Chenming Hu, Gene Hill, Michael H. Brodsky, Linda Milor, Michael Orshansky, Yeng-Kaung Peng
Publikováno v:
SPIE Proceedings.
Statistical characterization of gate CD variability of a production CMOS process reveals a large spatial intra-field component, strongly dependent on the local layout patterns. We present a novel measurement based characterization approach that is ca
Publikováno v:
SPIE Proceedings.
Deep submicron technology poses many difficult challenges. One of them is the optimization of the clock rate versus sub-threshold leakage trade-off. Top speed performance demands the shortest possible channel length for all transistors in the critica
Publikováno v:
Computer Integrated Manufacturing Systems. 10:169
A method of analyzing a failure of a sample, such as a wafer or a package unit made from a die sliced from the wafer, uses a computer aided design (CAD) tool in conjunction with a dual beam scanner and reverse engineering to improve the yield of the
Publikováno v:
1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference & Workshop ASMC 97 Proceedings; 1997, p33-36, 4p
Publikováno v:
1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings (Cat No97CH36023); 1997, pB29-B32, 4p