Zobrazeno 1 - 10
of 936
pro vyhledávání: '"Yee-Chia Yeo"'
Publikováno v:
Scientific Reports, Vol 7, Iss 1, Pp 1-9 (2017)
Abstract We developed a new digital etch process that allows precise etching of Germanium or Germanium-tin (Ge1−x Sn x ) materials. The digital etch approach consists of Ge1−x Sn x oxide formation by plasma oxidation and oxide removal in diluted
Externí odkaz:
https://doaj.org/article/c890dc39b6ee446f9ae6b0f5ddd28403
Autor:
Gerben Doornbos, Martin Holland, Georgios Vellianitis, Mark J. H. Van Dal, Blandine Duriez, Richard Oxland, Aryan Afzalian, Ta-Kun Chen, Gordon Hsieh, Matthias Passlack, Yee-Chia Yeo
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 4, Iss 5, Pp 253-259 (2016)
We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the equivalent oxide thickness EOT in conjunction with high-κ
Externí odkaz:
https://doaj.org/article/3f9a947ff28244ed8ba1c54803efcb7e
Autor:
Yuye Kang, Yi-Chiau Huang, Kwang Hong Lee, Shuyu Bao, Wei Wang, Dian Lei, Saeid Masudy-Panah, Yuan Dong, Ying Wu, Shengqiang Xu, Chuan Seng Tan, Xiao Gong, Yee-Chia Yeo
Publikováno v:
AIP Advances, Vol 8, Iss 2, Pp 025111-025111-7 (2018)
Strain relaxation of biaxially strained Ge1-xSnx layer when it is patterned into Ge1-xSnx fin structures is studied. Ge1-xSnx-on-insulator (GeSnOI) substrate was realized using a direct wafer bonding (DWB) technique and Ge1-xSnx fin structures were f
Externí odkaz:
https://doaj.org/article/9906f351723540bd99cb26b277df3333
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 3, Iss 3, Pp 86-87 (2015)
The increasing power consumption of integrated circuits is today the main impediment to the density scaling of integrated circuit technology. The reduction of supply voltage is the most effective way to reduce power; however, using modern transistors
Externí odkaz:
https://doaj.org/article/89f580b1151e4c9da0bb332de4b524b4
Publikováno v:
IEEE Journal of Emerging and Selected Topics in Power Electronics. 8:4270-4278
This article reports the design and the first experimental demonstration of the monolithically integrated over-current protection (OCP) circuit in GaN power converters. The design criteria and protection time estimation methods are proposed. Through
Publikováno v:
IEEE Transactions on Electron Devices. 67:2682-2689
A ladder transmission line model (LTLM) that features capability to eliminate parasitic metal resistance from contact metal and access electrodes, a simple fabrication process, and a sub- $10^{-{10}}\,\, \Omega \cdot $ cm2 resolution is demonstrated
Publikováno v:
IEEE Transactions on Electron Devices. 67:2690-2696
In the first part of this two-part article, a ladder transmission line model (LTLM), featuring elimination of parasitic metal resistances and high accuracy for extracting specific contact resistivity $\rho _{\text {c}}$ , is developed and verified by
Publikováno v:
IEEE Journal of Emerging and Selected Topics in Power Electronics. 8:31-41
This article reports the Au-free GaN power integration platform and a complete integration scheme from devices to functional subcircuits and to application-oriented GaN converter ICs. The design and experimental demonstration of all-GaN dc–dc conve
Autor:
Peter Ramvall, A. Devin Giddings, Yee-Chia Yeo, Aryan Afzalian, Ruey-Lian Hwang, T. Vasen, Matthias Passlack
Publikováno v:
ACS Applied Nano Materials. 2:1253-1258
Growth of ultrathin semiconducting nanowires (NWs) and incorporation of dopants suitable for future CMOS scaling targets (diameter
Autor:
Ying Wu, Sheng Luo, Wei Wang, Saeid Masudy-Panah, Dian Lei, Gengchiau Liang, Xiao Gong, Yee-Chia Yeo
Publikováno v:
Journal of Applied Physics; 12/14/2017, Vol. 122 Issue 22, p1-7, 7p