Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Ye-Seok Yang"'
Autor:
Ye Seok Yang, Sukkwang Park, Kun-Ok Ahn, Byoungjun Park, Dong Wook Lee, Sungwook Park, Myoung Kwan Cho, Byung Woo Kang, Sunghoon Cho
Publikováno v:
2011 3rd IEEE International Memory Workshop (IMW).
As the NAND flash market demand for larger capacity with low cost increases, the feature-size scaling and multi-level per bit have been developed. In this paper, we present the newly adopted operation algorithms and their results such as intelligent
Autor:
Sang-hoon Shin, Dongsuk Shin, Shin Deok Kang, Won-Joo Yun, Keun Soo Song, Ye Seok Yang, Dong Uk Lee, Won Jun Choi, Jin-Hong Ahn, Hyang Hwa Choi, Hyeng Ouk Lee, Nak Kyu Park, Sujeong Sim, Seung Wook Kwack, Young Ju Kim, Ji Yeon Yang, Hyung Wook Moon, Hyun-woo Lee, Kwan-Weon Kim, Young Kyoung Choi, Jung-Woo Lee, Young Jung Choi
Publikováno v:
ISSCC
We design a DLL that has a slew-rate controlled duty-cycle-correction (DCC) with a fully digital controlled duty-cycle-error detector and has the update gear circuit to shift update mode for low power consumption. The DLL is composed of a dual loop a
Autor:
Ye Seok Yang, Dong Uk Lee, Jung-Woo Lee, Shin Deok Kang, Young Jung Choi, Hyun-woo Lee, Kwan-Weon Kim, Sang-hoon Shin, Young Kyoung Choi, Nak Kyu Park, Won-Joo Yun, Hyeong Ouk Lee, Seung Wook Kwack
Publikováno v:
ISSCC
In this work, a multi-slew-rate output driver is developed to cope with the supply voltage variation and the different I/O component capacitance (denoted by CIO) condition. For accurate data transfer, it is necessary to reduce the design loss in the
Autor:
Young-Kyoung Choi, Won-Joo Yun, Ki-Chang Kwean, Won Jun Choi, Seung-Wook Kwack, Young-Jung Choi, Shin-Deok Kang, Sang-hoon Shin, Joong-Sik Kih, Hyong-Uk Moon, Hyun-woo Lee, Kwan-Weon Kim, Hyang-Hwa Choi, Hyeng-Ouk Lee, Nak-Kyu Park, Jung-Woo Lee, Young Ju Kim, Dong Uk Lee, Jin-Hong Ahn, Ye-Seok Yang
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down co
Autor:
Dong Uk Lee, Shin Deok Kang, Nak Kyu Park, Hyun Woo Lee, Young Kyoung Choi, Jung Woo Lee, Seung Wook Kwack, Hyeong Ouk Lee, Won Joo Yun, Sang Hoon Shin, Kwan Weon Kim, Young Jung Choi, Ye Seok Yang
Publikováno v:
2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p280-613, 334p
Autor:
Won-Joo Yun, Hyun-Woo Lee, Young-Ju Kim, Won-Jun Choi, Sang-Hoon Shin, Hyang-Hwa Choi, Hyeng-Ouk Lee, Shin-Deok Kang, Hyong-Uk Moon, Seung-Wook Kwack, Dong-Uk Lee, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Ki-Chang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Joong-Sik Kih, Ye-Seok Yang
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference; 2006, p323-326, 4p
Autor:
Dong Wook Lee, Sunghoon Cho, Byung Woo Kang, Sukkwang Park, Byoungjun Park, Myoung Kwan Cho, Kun-Ok Ahn, Ye Seok Yang, Sung Wook Park
Publikováno v:
2011 3rd IEEE International Memory Workshop (IMW); 2011, p1-2, 2p