Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Yasutaka Nakashiba"'
Autor:
Shinichi Uchida, Akio Ono, Tetsuya Iida, Yasutaka Nakashiba, Teruhiro Kuwajima, Kuramoto Takafumi, Takuho Kamada, Risho Koh, Akira Matsumoto
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
A novel Circuit Under on-chip-inductor structure (CUL) including high-Q inductor (Q peak > 19) formed in the redistribution layer (RDL) is proposed to reduce the chip-size of RF embedded MCUs/SoCs. A design methodology for the CUL implementation with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce44514897231006be51726c0a63811b
https://doi.org/10.1109/edtm.2019.8731084
https://doi.org/10.1109/edtm.2019.8731084
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:101-106
We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9603c8a8fb6891f0ef599c0b77c9a02a
https://doi.org/10.1109/jssc.2002.806285
https://doi.org/10.1109/jssc.2002.806285
Autor:
Kaoru Ishihara, Hirokazu Nagase, Tadashi Maeda, Yasutaka Nakashiba, Shinichi Uchida, Shunichi Kaeriyama, Koichi Takeda
Publikováno v:
2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD).
A face-to-face chip stacking isolator structure, which makes it easy to enhance the insulation voltage, is proposed. Transmitter (Tx) and receiver (Rx) chips, each of which has a coil, are stacked and communicate through a magnetic coupling of the co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::143832a30a1dc92cd5d7eee763d75926
https://doi.org/10.1109/ispsd.2014.6856071
https://doi.org/10.1109/ispsd.2014.6856071
Autor:
Fuyuki Okamoto, Yuki Fujimoto, Masayuki Furumiya, Keisuke Hatano, Yasutaka Nakashiba, Michio Yotsuyanagi
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 84:28-35
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8df65f0922561b48bb45973b88e4921
https://doi.org/10.1002/ecjb.1055.abs
https://doi.org/10.1002/ecjb.1055.abs
Autor:
T. Nakano, Yasuaki Hokari, Y. Taniji, Yukiya Kawakami, D. Syohji, Satoshi Katoh, T. Satoh, Nobukazu Teranishi, K. Orihara, Yasutaka Nakashiba, S. Suwazono, Masayuki Furumiya, H. Utsumi, M. Morimoto, N. Mutoh
Publikováno v:
IEEE Transactions on Electron Devices. 48:1922-1928
A 30 frames/s 2/3-in 1.3 M-pixel progressive scan interline-transfer charge-coupled device (IT-CCD) image sensor has been developed for video and digital still-camera applications. To obtain high frame-rate images, a 49-MHz driving horizontal CCD (H-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95fabe33df771718fdf4a474bc95be5c
https://doi.org/10.1109/16.944178
https://doi.org/10.1109/16.944178
Autor:
Yasutaka Nakashiba, Toshishige Yamada, Masayuki Furumiya, N. Mutoh, S. Suwazono, Yasuaki Hokari, A. Tanabe, T. Nakano, Keisuke Hatano, Satoshi Katoh, Satoshi Uchiya, H. Utsumi, Yukiya Kawakami, S. Kawai, D. Syohji, Nobukazu Teranishi, K. Orihara, M. Morimoto, Y. Taniji
Publikováno v:
IEEE Transactions on Electron Devices. 48:222-230
A 1/2-in 1.3 M-pixel progressive-scan interline-transfer charge-coupled-device (IT-CCD) image sensor has been developed for small, low-power mega-pixel digital still cameras (DSCs). The pixel size as small as 5 /spl mu/m square makes small-size progr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62e76f09124a90ebbea364837e56c88d
https://doi.org/10.1109/16.902720
https://doi.org/10.1109/16.902720
Autor:
Yuki Fujimoto, Masayuki Furumiya, Yasutaka Nakashiba, Yoshinori Muramatsu, Hiroaki Ohkubo, Fuyuki Okamoto, Susumu Kurosawa
Publikováno v:
IEEE Transactions on Electron Devices. 48:2221-2227
A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-/spl mu/m CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a7fe39c45ce762e9bae15e0fa9e567a
https://doi.org/10.1109/16.954458
https://doi.org/10.1109/16.954458
Autor:
Yasuaki Hokari, Satoshi Uchiya, N. Mutoh, K. Arai, T. Kawasaki, H. Utsumi, Tsuyoshi Nagata, Nobukazu Teranishi, Keisuke Hatano, Akiyoshi Kohno, Yasutaka Nakashiba, Masayuki Furumiya, T. Nakano, Ichiro Murakami
Publikováno v:
IEEE Transactions on Electron Devices. 47:1566-1572
New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the pho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35e95d4005d42a636ad89f4ae0fe6390
https://doi.org/10.1109/16.853032
https://doi.org/10.1109/16.853032
Autor:
Yasutaka Nakashiba, M. Nishimura, I. Akiyama, Nobukazu Teranishi, K. Arai, A. Toyoda, Yasuaki Hokari, Yukiya Kawakami, Keisuke Hatano, S. Kawai, K. Orihara, M. Ohbo, Akiyoshi Kohno, N. Mutoh, K. Chiba, T. Nakano, M. Morimoto
Publikováno v:
IEEE Transactions on Electron Devices. 42:50-57
A 1-inch 2-million pixel FIT-CCD image sensor for HDTV has been developed, which features a tungsten photo-shield and horizontal CCD (H-CCD) shunt wiring. Tungsten photo-shield, which has low reflectance and good step coverage characteristics, reduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba959ec361ea60a29e74fe7ff19c0f44
https://doi.org/10.1109/16.370036
https://doi.org/10.1109/16.370036
Autor:
Yasutaka Nakashiba, Hiroaki Ohkubo, Hiroaki Namba, Shinichi Uchida, Kuramoto Takafumi, Kenji Hayashi, Takasuke Hashimoto, Masayuki Furumiya
Publikováno v:
2012 Asia Pacific Microwave Conference Proceedings.
This paper describes the optimization method on choice of the metal layers and the Si substrate structure about the 3-Dimantional(3D) vertical solenoid inductor on the CMOS process. The optimization of metal layers that constituted 3D structure induc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10312cacffb1a65fbb553749b80306ff
https://doi.org/10.1109/apmc.2012.6421891
https://doi.org/10.1109/apmc.2012.6421891