Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Yasumoto Tomita"'
Publikováno v:
IPDPS Workshops
With the emergence of AI, we observe a surge of interest in applying machine learning to traditional HPC workloads. An example is the use of surrogate models that approximate the output of scientific simulations at very low latency. However, such a b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::566cef75175835f34aff0b0abba75edf
https://doi.org/10.1109/ipdpsw50202.2020.00134
https://doi.org/10.1109/ipdpsw50202.2020.00134
Autor:
Hiroshi Okano, S. Satoh, Yasumoto Tomita, Hitoshi Sakurai, Ryuichi Nishiyama, Tetsutaro Hashimoto, Yasushi Kakimura, Shinichiro Shirota, Yukihito Kawabe, Hideo Yamashita, Kunihiko Tajiri, Michiharu Hara
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:1028-1037
On-die supply-voltage droops attributed to workload variations degrade the performance of high-performance microprocessors. An adaptive-clocking-control circuit was implemented for mitigating the adverse impact of supply-voltage droops on processor p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8fd18a6c9887a083c6a557ffe05506c
https://doi.org/10.1109/jssc.2017.2777101
https://doi.org/10.1109/jssc.2017.2777101
Autor:
Atsushi Ike, Satoshi Tanabe, Kyosuke Maeda, Yasumoto Tomita, Akira Nakagawa, Takuya Fukagai, Koichi Shirahata
Publikováno v:
ICIP
We realized a speed-up of an object detection neural network with GPU. We improved the object detection speed of faster R-CNN [1], which is one of the most commonly used detection networks [2]. The speed of the original faster R-CNN (py - faster - rc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a9b7553ed4c709eeb3c9767f3a3d362
https://doi.org/10.1109/icip.2018.8451814
https://doi.org/10.1109/icip.2018.8451814
Publikováno v:
International Journal of Networking and Computing, 8 (2
Vrije Universiteit Brussel
CANDAR
Vrije Universiteit Brussel
CANDAR
Recent state-of-the-art deep reinforcement learning algorithms, such as A3C and UNREAL, are designed to train on a single device with only CPU's. Using GPU acceleration for these algorithms results in low GPU utilization, which means the full perform
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8d26349b8f2cd1a59fff98f9c3e3b768
http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/298534
http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/298534
Autor:
Takuya Fukagai, Koichi Shirahata, T. Hashimoto, Yasumoto Tomita, Jun Sun, Satoshi Naoi, Song Wang, Sun Li, Atsushi Ike, Wei Fan
Publikováno v:
ICME
Nowadays the CNN is widely used in practical applications for image classification task. However the design of the CNN model is very professional work and which is very difficult for ordinary users. Besides, even for experts of CNN, to select an opti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a0369cbc9087a91830ef07ec93ac4ae
https://doi.org/10.1109/icme.2017.8019347
https://doi.org/10.1109/icme.2017.8019347
Autor:
Hitoshi Sakurai, Hideo Yamashita, Yukihito Kawabe, Hiroshi Okano, Yasumoto Tomita, S. Satoh, Michiharu Kara, Tetsutaro Hashimoto, Ryuichi Nishiyama, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota
Publikováno v:
2017 Symposium on VLSI Circuits.
This paper presents an adaptive clocking control circuit to mitigate the processor performance degradation due to on-die supply voltage droops. The circuit utilizes multi-path TDC to reduce quantization errors and thermometer code-based data processi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fe59ff5aab104cbc5fec5565e23aa995
https://doi.org/10.23919/vlsic.2017.8008569
https://doi.org/10.23919/vlsic.2017.8008569
Publikováno v:
MLSP
Training deep neural networks requires a large amount of memory, making very deep neural networks difficult to fit on accelerator memories. In order to overcome this limitation, we present a method to reduce the amount of memory for training a deep n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7676560ab3c2cf1d6616d30666682b32
https://doi.org/10.1109/mlsp.2016.7738869
https://doi.org/10.1109/mlsp.2016.7738869
Autor:
Hidetoshi Matsumura, Yasumoto Tomita, Sugimura Masahiko, David Thach, Yasuhiro Watanabe, Takashi Shimizu, Hironobu Yamasaki, Takayuki Baba, Takashi Miyoshi, Atsushi Ike
Publikováno v:
VLSI Circuits
We propose and demonstrate an FPGA-accelerated partial-image-matching engine for massive media-data searching systems. To take advantage of FPGA, a highly parallelized and pipelined architecture with an application-specific calculation was adopted. O
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af5c4bac380b1a71accf88adbe1d2a7c
https://doi.org/10.1109/vlsic.2016.7573489
https://doi.org/10.1109/vlsic.2016.7573489
Autor:
Yasuhiro Watanabe, Yasumoto Tomita, Hironobu Yamasaki, Takayuki Baba, Sugimura Masahiko, Hidetoshi Matsumura
Publikováno v:
WACV
In this paper, we introduce an FPGA-accelerated partial image retrieval engine, suitable for a visualized document search system. To achieve efficient sharing and reuse of digitized documents, this system has the function of partial duplicate image r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5a438bdbba08281aad0a985cb489840
https://doi.org/10.1109/wacv.2016.7477662
https://doi.org/10.1109/wacv.2016.7477662
Autor:
Nestor Tzartzanis, Mariko Sugawara, Masaya Kibune, Yoshiyasu Doi, Yukito Tsunoda, Scott McLeod, Anders Kristensson, H. Tamura, Subodh M. Reddy, Satoshi Ide, William F. Walker, Tetsuji Yamabana, Kouichi Kanda, Nikola Nedovic, Satoshi Matsubara, Samir Parikh, Junji Ogawa, Takayuki Hamada, T. Yamamoto, Tadashi Ikeuchi, Takayuki Shibasaki, Naoki Kuwata, Yasumoto Tomita
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:2016-2029
A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s inter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cc5fda0900971ac3eb33240e0b3418d
https://doi.org/10.1109/jssc.2010.2057970
https://doi.org/10.1109/jssc.2010.2057970