Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Yasuko Eckert"'
Publikováno v:
NOCS
The performance of graphics processing units (GPU) workloads can be sensitive to the various clock domains which are dynamically tunable in modern GPUs. In this work, we observe that GPU application performance is sensitive towards NoC clock frequenc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81936e7a8df88295e4b5303b59f1ae44
https://doi.org/10.1145/3479876.3481590
https://doi.org/10.1145/3479876.3481590
Publikováno v:
PACT
Graphics Processing Units (GPUs) concurrently execute thousands of threads, which makes them effective for achieving high throughput for a wide range of applications. However, the memory wall often limits peak throughput. GPUs use caches to address t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0db88a41f2fbfc1fb247cc1742c52fb0
https://doi.org/10.1145/3410463.3414623
https://doi.org/10.1145/3410463.3414623
Autor:
Yasuko Eckert, Patel Chintan S, Smith Alan Dodson, Natalie Enright Jerger, Morton Eric Christopher, Jieming Yin, Mark Oskin, Gabriel H. Loh, Sethumurugan Subhash
Publikováno v:
HPCA
There has been a lot of recent interest in applying machine learning (ML) to the design of systems, which purports to aid human experts in extracting new insights leading to better systems. In this work, we share our experiences with applying ML to i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9153348d597928ef00686d4b06c85080
https://doi.org/10.1109/hpca47549.2020.00058
https://doi.org/10.1109/hpca47549.2020.00058
Autor:
Gabriel H. Loh, Lifeng Nai, Ramyad Hadidi, Hyesoon Kim, Onur Kayiran, Nuwan Jayasena, Hyojong Kim, Yasuko Eckert
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 15:1-23
To exploit parallelism and scalability of multiple GPUs in a system, it is critical to place compute and data together. However, two key techniques that have been used to hide memory latency and improve thread-level parallelism (TLP), memory interlea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6af40699cb29b9a47d654e45620c4eb1
https://doi.org/10.1145/3232521
https://doi.org/10.1145/3232521
Publikováno v:
ICS
Near-memory processing or processing-in-memory (PIM) is regaining a lot of interest recently as a viable solution to overcome the challenges imposed by memory wall. This trend has been mainly fueled by the emergence of 3D-stacked memories. GPUs are t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b3627ff0ef554fd24a96e618832cb336
https://doi.org/10.1145/2925426.2926282
https://doi.org/10.1145/2925426.2926282
Publikováno v:
MEMSYS
Silicon interposer technology is promising for large-scale integration of memory within a processor package. While past work on vertical, 3D-stacked memory allows a stack of memory to be placed directly on top of a processor, the total amount of memo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b66d9a5feb1b7d73c8b4aa49560ccd3
https://doi.org/10.1145/2818950.2818951
https://doi.org/10.1145/2818950.2818951
Publikováno v:
SIGMETRICS
Idle power is a significant contributor to overall energy consumption in modern multi-core processors. Cores can enter a full-sleep state, also known as C6, to reduce idle power; however, entering C6 incurs performance and power overheads. Since powe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6dff1779107aacd8ac1a8fb1d307072
https://doi.org/10.1145/2591971.2592017
https://doi.org/10.1145/2591971.2592017
Publikováno v:
HPCA
The steadily increasing sizes of main memory capacities require corresponding increases in the processor's translation lookaside buffer (TLB) resources to avoid performance bottlenecks. Large operating system page sizes can mitigate the bottleneck wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4dc6596c26c6cc0eaf1f9732fb35d66b
https://doi.org/10.1109/hpca.2014.6835964
https://doi.org/10.1109/hpca.2014.6835964
Publikováno v:
ISLPED
The limited utility of voltage scaling in nano-scale technologies has led high-performance processors to rely increasingly on frequency scaling for power management. However, frequency scaling provides only a linear dynamic power reduction.In this pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::433430ff7bd48193934e8dadd3ed5f1e
https://doi.org/10.1145/2333660.2333748
https://doi.org/10.1145/2333660.2333748