Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Yaroku Sugiyama"'
Autor:
Takahisa Hiraide, Akira Kanuma, Tsuyoshi Mochizuki, Masahiro Yanagida, Shigeru Nagasawa, Chihiro Endoh, Yutaka Isoda, Yaroku Sugiyama, Takeshi Kono, Osamu Sugawara, Hitoshi Yamanaka, Kazunobu Adachi, Noriyuki Ito, Eizo Ninoi, Daisuke Maruyama
Publikováno v:
ASP-DAC
This paper present a case-study of delay defect screening applied to Fujitsu 2.16GHz SPARC64 microprocessor. A nonrobust delay test is used while each test vector is compacted to detect multiple transition faults in a standard scan-based design targe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2032801798ea402f995538c56aaac125
https://doi.org/10.1145/1118299.1118387
https://doi.org/10.1145/1118299.1118387
Publikováno v:
ICCAD
This work presents a new non-robust delay fault test generation method for the purpose of screening delay defects of microprocessors with fewer test vectors. It is important to reduce the number of test vectors in order to reduce test time, memory us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d4c7cd1d1a0c4671c49a3b23c550743
https://doi.org/10.1109/iccad.2004.1382701
https://doi.org/10.1109/iccad.2004.1382701
Autor:
Hiroaki Komatsu, H. Hamamura, Noriyuki Ito, Hiroyuki Sugiyama, Yaroku Sugiyama, Y. Tanamura, Ryoichi Yamashita
Publikováno v:
ICCD
We present a physical design methodology that was applied to the design of Fujitsu 1.3 GHz SPARC 64 microprocessor. A tool-set called GigaGate was developed based on this methodology. The goal of GigaGate is to support the design team to complete the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::437a70cc9ec84d4c3ae23c556f529ceb
https://doi.org/10.1109/iccd.2003.1240896
https://doi.org/10.1109/iccd.2003.1240896