Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Yao Sheng Hu"'
Publikováno v:
A-SSCC
In this paper, a low-power detective open-loop dynamic (DeOLD) system buffer codesigned with a SAR ADC that is pertinent for zero-capacitor touch with a display driver integration (TDDI) system is proposed. The proposed DeOLD system buffer not only b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fbe189384ed31ed5f5d68e45aaa639d
https://doi.org/10.1109/jssc.2019.2921481
https://doi.org/10.1109/jssc.2019.2921481
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 63:1166-1170
This brief presents a 0.9-V 8-bit 800-MS/s energy-efficient two-step successive-approximation register (SAR) analog-to-digital converter (ADC) without an inter-stage residue amplifier. A charge-sharing technique is used to avoid large static current
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ffb2e2e9aa7277e485f1f1d25b3ea0f
https://doi.org/10.1109/tcsii.2016.2608908
https://doi.org/10.1109/tcsii.2016.2608908
Autor:
Yao-Sheng Hu, 胡耀升
107
This thesis concludes author’s researches in the topic of “the applications of the subranging successive-approximation register (SAR) analog-to-digital (ADC) with the skipping switching method”. The applications includes recently popul
This thesis concludes author’s researches in the topic of “the applications of the subranging successive-approximation register (SAR) analog-to-digital (ADC) with the skipping switching method”. The applications includes recently popul
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/g87c2s
Publikováno v:
A-SSCC
This paper presents an 89.55dB-SFDR 2.55μW 12-bit lMS/s SAR-assisted SAR ADC in 40nm CMOS at a 0.7V supply. The proposed weight-split compensation provides an accurate mapping between capacitor mismatch and digital weight to take advantages of both
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26594798603c111184fef1aaf75052ad
https://doi.org/10.1109/asscc.2018.8579310
https://doi.org/10.1109/asscc.2018.8579310
Publikováno v:
2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2c0e3c24440586c129d0b43f9881a4ee
https://doi.org/10.1109/asscc.2018.8579298
https://doi.org/10.1109/asscc.2018.8579298
Akademický článek
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Publikováno v:
2017 Symposium on VLSI Circuits.
This paper presents a 510nW 12-bit 200kS/s SAR-assisted SAR ADC in 40nm CMOS at 0.7V supply. A re-switching technique is proposed to suppress DNL spikes so that the size of DAC capacitor array can be minimized to reduce switching energy. A set of 2-w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b0d57965a531e578ce433bfcaa12b6bd
https://doi.org/10.23919/vlsic.2017.8008493
https://doi.org/10.23919/vlsic.2017.8008493
Publikováno v:
Key Engineering Materials. 633:348-351
Corundum-based castables were prepared by using tabular corundum, micropowder of MgAl2O4spinel and calcium aluminate cement as raw materials, as well as the addition of dispersion agent and retarder. The effect of spinel contents on physical properti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::222642d82cb0b120158da2fb9ffccf21
https://doi.org/10.4028/www.scientific.net/kem.633.348
https://doi.org/10.4028/www.scientific.net/kem.633.348
Publikováno v:
A-SSCC
This paper presents an energy-efficient 12-bit 200kS/s subranging SAR ADC for multi-touch sensing applications. In order to reduce DAC power consumption, an energy-curve reshape technique is proposed to fit the switching energy curve to the character
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdc3d9bde8e12564990bc4df25dbf36a
https://doi.org/10.1109/asscc.2016.7844157
https://doi.org/10.1109/asscc.2016.7844157
Publikováno v:
A-SSCC
An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e98e60087f877b494793725b7e52dc1
https://doi.org/10.1109/asscc.2016.7844140
https://doi.org/10.1109/asscc.2016.7844140