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pro vyhledávání: '"Yanzhong Ma"'
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 2, Iss 4 (2019)
In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% o
Externí odkaz:
https://doaj.org/article/3aeb9decb89f459099f790abf23b1cc9
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXIV.
In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01a0fba40b05f33d882f4b19e26fb917
https://doi.org/10.1117/12.2550947
https://doi.org/10.1117/12.2550947
Autor:
Yi Zhou, Le Yang, Yanzhong Ma, Chi Chen, Xiaoye Ding, Yangtze Memory Technologies Co, ., Ltd, Wuhan, China, Sicong Wang, Skyverse Ltd, Shenzhen, China
Publikováno v:
Journal of Microelectronic Manufacturing, Vol 2, Iss 4 (2019)
In traditional 3D NAND design, peripheral circuit accounts for 20-30% of the chip real-estate, which reduces the memory density of flash memory. As 3D NAND technology stacks to 128 layers or higher, peripheral circuits may account for more than 50% o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::38a59c5f70a646f17f3d3ef01de92c98
http://www.jommpublish.org/p/42/#
http://www.jommpublish.org/p/42/#