Výsledky vyhledávání - "Yann Carminati"

RAPIDO Testing of Assisted Write and Read operations for Ultra-Low Power SRAMs

Autor: Joseph Nguyen, Turgis, D., David Bonciani, Brice Lhomme, Yann Carminati, Olivier Callen, Guillaume Guirleo, Lorenzo Ciampolini, gerard ghibaudo

Publikováno v: HAL
W07 International Workshop on Emerging Memory Solutions
W07 International Workshop on Emerging Memory Solutions, Mar 2016, Dresden, Germany

W07.12.4; International audience

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::a96c1d2dfd24be84869a2d46fe15cca8
https://hal.archives-ouvertes.fr/hal-02051768

Zobrazit plný text záznamu

Silicon thickness monitoring strategy for FD-SOI 28nm technology

Autor: P. Normandon, Franck Arnaud, Yann Carminati, Antoine Cros, David Petit, Julien Rosa, Frederic Monsieur

Publikováno v: Proceedings of the 2015 International Conference on Microelectronic Test Structures.

The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::71348888debe0fa848ff95c18266776a
https://doi.org/10.1109/icmts.2015.7106110

Zobrazit plný text záznamu

Analysis of process impact on local variability thanks to addressable transistors arrays

Autor: Flore Kergomard, Yann Carminati, Thomas Quemerais, A. Bajolet, Franck Arnaud, Julien Rosa, Nicolas Planes, Antoine Cros, P. Normandon, David Petit

Publikováno v: 2014 International Conference on Microelectronic Test Structures (ICMTS).

We designed an addressable transistors array to analyse local variability at the wafer scale. On FDSOI substrates, we measure no impact of the silicon thickness variations on short channel transistors, and demonstrate that the impact on large area tr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c65772b2cd5697b42d2fe5d7c5269607
https://doi.org/10.1109/icmts.2014.6841498

Zobrazit plný text záznamu

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter

Autor: Bertrand Borot, Yann Carminati, Thierry Burdeau, Sylvain Clerc, Brice Lhomme, Olivier Callen

Publikováno v: ESSCIRC

Following the circuit integration trend, the process monitoring structures need to predict the production circuits reliability while keeping test time small and preserving the wafer area. The design presented monitors a 40nm CMOS bitcell failure evol

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::44013d8d2b5b8c70b2550e2e7fc4d94b
https://doi.org/10.1109/esscirc.2010.5619718

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání