Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Y.T. Loh"'
Autor:
Shiwei Chen, Wan Rong Sia, Leon J.W. Tang, Akshamal M. Gamage, Wharton O.Y. Chan, Feng Zhu, Wanni Chia, Madeline S.S. Kwek, Pui San Kong, Beng Lee Lim, Randy Foo, Wei Lun Ng, Adrian H.J. Tan, Shan He, Abigail Y.T. Loh, Dolyce H.W. Low, Gavin J.D. Smith, Lewis Z. Hong, Lin-Fa Wang
Publikováno v:
Cell Reports, Vol 43, Iss 10, Pp 114767- (2024)
Externí odkaz:
https://doaj.org/article/cad1b96544b740a29443d2a25c2296f4
Publikováno v:
Hippocampus. 14:87-98
At 4 h during pilocarpine-induced status epilepticus (DPISE) in rat, protein kinase C (PKC)beta1, PKCbeta2, and PKCgamma were induced at the border between the stratum oriens and alveus (O/A border) of CA1 in the hippocampus. Induced PKCgamma was col
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc6a1065265f8675c16efa573d4bcb80
https://doi.org/10.1002/hipo.10156
https://doi.org/10.1002/hipo.10156
Autor:
Klaus Schruefer, Anastasios A. Katsetos, Chih-Yung Lin, Terence B. Hook, Fu Tai Liou, Nivo Rovedo, Jen-Kon Chen, Zhijian Yang, Tze Chiang Chen, C.H. Liu, Ming T. Lee, Y.T. Loh, C. Wann
Publikováno v:
Japanese Journal of Applied Physics. 41:2423-2425
The physical mechanism responsible for negative bias temperature instability (NBTI), which is basic to the minimization of this degradation mode, is investigated, and an analytical model is developed accordingly. Experiments with 1.7 nm to 3.3 nm gat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2606692d36ef765152781bec0b39c8d
https://doi.org/10.1143/jjap.41.2423
https://doi.org/10.1143/jjap.41.2423
Publikováno v:
Acta biomaterialia. 7(2)
An important requirement for a bone tissue engineering scaffold is a stiffness gradient that mimics that of native bone. Such scaffolds can be achieved by controlling their structure and porosity and are termed functionally graded scaffolds (FGS). Cu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::795bf9ed7a8af0b9b1e2757e443489c5
https://pubmed.ncbi.nlm.nih.gov/20883840
https://pubmed.ncbi.nlm.nih.gov/20883840
Publikováno v:
International Electron Devices and Materials Symposium.
Silicon-on-Insulator (SOI) is becoming more attractive for enhancing performance as MOSFET physical dimensions are scaled down. In this work, a 0.5 micron process using bonded SOI material is compared to bulk CMOS. The comparisons include electrical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9470d0fbfe2404e86c04e2bd81164cf
https://doi.org/10.1109/edms.1994.771270
https://doi.org/10.1109/edms.1994.771270
Autor:
Y.S. Hsieh, G. Braithwaite, J.H. Ho, J.K. Chen, C.C. Huang, Ming-Ren Lin, N. Gerrish, Y.T. Loh, F. Singaporewala, Ariel Liu, W.T. Shiau, Y.Y. Chiang, J.R. Hwang, Richard Hammond, H.K. Lee, Mayank T. Bulsara, T.P. Chen, S.C. Chien, T.M. Shen, M. Currie, Qi Xiang, S.M. Ting, F. Wen, A. Lochtefeld
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2509726fa79ce52f08a712f14e188723
https://doi.org/10.1109/vlsit.2003.1221107
https://doi.org/10.1109/vlsit.2003.1221107
Autor:
Yu-Yin Lin, K.T. Huang, Tung-Ming Pan, Fu-Tai Liou, M. Huang, C.J. Kao, A.Y. Liang, Chiung-Sheng Hsiung, W.Y. Hsieh, P.W. Yen, Jen-Kon Chen, S.H. Lin, C.H. Liu, S.C. Chien, J.H. Lee, S. Huang-Lu, Wen-Tung Chang, Y.J. Chang, M.G. Chen, Y.C. Sheng, Y.T. Loh, Chen-Chung Hsu, Hsiu-Shan Lin
Publikováno v:
2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
Ultra-thin gate dielectrics processed by remote plasma nitridation (RPN) of N/sub 2/O-grown oxides subsequently followed by NO RTA treatment (N/sub 2/O+RPN+NO process) are reported for the first time as a means to extend the reliability scaling limit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f818b9cfb1cf0d69e3d2839092d7ba66
https://doi.org/10.1109/relphy.2002.996646
https://doi.org/10.1109/relphy.2002.996646
Publikováno v:
Proceedings. IEEE International SOI Conference.
As it becomes more difficult to increase MOSFET current drive through standard scaling techniques, other methods to improve performance are being pursued. One such technique is to use silicon-on-insulator (SOI) starting wafers. Performance enhancemen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a11f12214f29aaafd95888796f44c146
https://doi.org/10.1109/soi.1994.514225
https://doi.org/10.1109/soi.1994.514225
Publikováno v:
Hippocampus; 2004, Vol. 14 Issue 1, p87-98, 12p
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