Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Y. Morimasa"'
Autor:
A. Oishi, M. Kido, Ryota Katsumata, K. Ohno, Y. Okayama, K. Oota, M. Saito, Y. Takegawa, R. Hasumi, T. Yokoyama, Naoki Nagashima, Y. Morimasa, M. Iwai, Y. Sogo, T. Komoda, T. Sanuki, T. Komoguchi, M. Tamura, Hisao Yoshimura, T. Noguchi, Takashi Kinoshita, K. Kasai, Hideaki Aochi, K. Hiyama, Fumiyoshi Matsuoka, K. Fukasaku, T. Matsumoto, Hiroyasu Tanaka, Y. Okamoto
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
For the first time, a deep trench based embedded DRAM cell for 45nm node system on a chip (SoC) applications is presented. We achieve both high data retention time and full compatibility with logic process, while scaling eDRAM cell down to 0.069/spl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c51e3b99b539d28db9de8e62daaef363
https://doi.org/10.1109/.2005.1469193
https://doi.org/10.1109/.2005.1469193
Autor:
Hisao Yoshimura, Y. Takegawa, T. Sanuki, Takashi Kinoshita, S. Aota, Kazumasa Sunouchi, T. Noguchi, Y. Morimasa, K. Isobe, M. Iwai, R. Hasumi, A. Oishi
Publikováno v:
IEEE International Electron Devices Meeting 2003.
In this work, we investigated the scalability of strained Si technology. The impact of scaling source/drain length (L/sub SD/) on electrical characteristics was studied for the first time. Drive current enhancement of strained PMOSFET usually disappe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef72fe82303a67f2bb25dc9a74d6039e
https://doi.org/10.1109/iedm.2003.1269167
https://doi.org/10.1109/iedm.2003.1269167
Autor:
Mariko Takayanagi, T. Komoda, Daisuke Matsushita, Y. Takegawa, M. Iwai, Kazuhiro Eguchi, T. Sanuki, Kazumasa Sunouchi, T. Noguchi, Kazunari Ishimaru, Kouichi Muraoka, A. Oishi, Y. Morimasa
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
This paper describes the first 45nm Node CMOS technology (CMOS6) with optimized Vdd, EOT and BEOL parameters. For this technology to be applicable from high performance CPU to mobile applications, three sets of core devices are presented which are co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::caaa9a6f20835f78dfea4808646330f7
https://doi.org/10.1109/vlsit.2004.1345364
https://doi.org/10.1109/vlsit.2004.1345364
Autor:
T. Itoh, Kazumasa Sunouchi, Y. Morimasa, H. Yamasaki, T. Sanuki, M. Hamaguchi, M. Iwai, T. Komoda, T. Noguchi, K. Oouchi, Y. Takegawa, K. Matsuo, Toshihiko Iinuma, A. Oishi
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
High performance CMOSFET process design for 45nm generation is demonstrated. Activation process policy is shown for the first time to achieve high performance source and drain extension (SDE) junction, high gate activation and defect-less source and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1372a815d6599bb4e50621784dcdd6d2
https://doi.org/10.1109/vlsit.2004.1345458
https://doi.org/10.1109/vlsit.2004.1345458
Autor:
Y. Morimasa, H. Okano, J. Kumagai, Hidetoshi Koike, H. Sato, T. Shimabukuro, K. Hiyama, H. Ishiuchi, Hideaki Harakawa, H. Naruse, O. Yakabe, Koichi Kokubun, S. Yoshida, K. Tomioka, H. Takato, H. Kamijo, S. Kato, T. Yamamoto, M. Tamaoki, M. Tanaka
Publikováno v:
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).
This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4cbdccbc5e20fd127dc8005ebee992c2
https://doi.org/10.1109/vtsa.1999.786045
https://doi.org/10.1109/vtsa.1999.786045
Autor:
H. Takato, N. Iwabuchi, Takayasu Sakurai, Koichi Kokubun, Y. Morimasa, N. Yanagiya, M. Kishida, Takeshi Yoshida, M. Tanaka, T. Noguchi, J. Kumagai, T. Hashimoto, K. Hiyama, H. Naruse, Y. Takasu, H. Ishiuchi, H. Ohtsuka, A. Nomachi, T. Miyamae
Publikováno v:
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
A new fabrication method for embedded DRAM of 0.18 /spl mu/m generation is proposed, which realizes full compatibility with logic process such as Co salicide, dual work function gate, small thermal budget and metalization, and introduces Self-aligned
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1078120acba16e33a788f7eb4a5cca79
https://doi.org/10.1109/cicc.2000.852618
https://doi.org/10.1109/cicc.2000.852618
Akademický článek
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Akademický článek
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Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Autor:
K. Nakayama, Naoki Nagashima, N. Nishiyama, J. Idebuchi, Hisao Yoshimura, T. Sanuki, Y. Takegawa, O. Fujii, K. Oota, K. Matsuo, H. Ito, H. Fukui, R. Yamaguchi, Masanobu Saito, Fumiyoshi Matsuoka, Y. Takasu, Y. Morimasa, Hiroyasu Tanaka, M. Iwai, Ichiro Mizushima
Publikováno v:
Scopus-Elsevier
For the first time, a novel CMOSFET structure in substrate strained-Si of lang100rang-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by hig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::757bdcd63ddfcae710b45f3b35cf8810
http://www.scopus.com/inward/record.url?eid=2-s2.0-33847747032&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-33847747032&partnerID=MN8TOARS
