Zobrazeno 1 - 10
of 56
pro vyhledávání: '"Xuejie SHI"'
Autor:
Xuejie SHI, Liming WANG, Jiahui LI, Zefeng TIAN, Shan SUN, Yanmin QI, Liping YOU, Yuanqing MA
Publikováno v:
Haiyang Kaifa yu guanli, Vol 40, Iss 10, Pp 104-113 (2023)
This paper analyzed the horizontal distribution and limitation of DIN, PO4-P and SiO3-Si based on the four surveys of Miaodao Archipelago sea area in August and October of 2018, April and June of 2019. The results showed that the concentration of DIN
Externí odkaz:
https://doaj.org/article/7a0c39236bf74ccca2d61525257aa3d2
Publikováno v:
Haiyang Kaifa yu guanli, Vol 40, Iss 6, Pp 85-92 (2023)
Based on the environmental monitoring data of Laizhou Bay in May (spring) and October (autumn), 2020, this paper had studied the spatial distribution characteristics of inorganic nitrogen (DIN) and reactive phosphate (DIP), the condition of seawater
Externí odkaz:
https://doaj.org/article/fbf829385f694e44978ea3dfd9d953af
Publikováno v:
ACS Omega. 7:12048-12055
Inulin is used as an important food ingredient, widely used for its fiber content. In this study the operational extraction variables to obtain higher yields of inulin from Jerusalem artichoke tubers, as well as the optimal conditions, were studied.
Publikováno v:
Microelectronics Journal. 85:1-5
In this paper, ideal Technology Computer Aided Design (TCAD) simulation is carried out for small size FinFET transistors. The definition of device critical dimensions is close to the 4th generation FinFET. The source/drain (s/d) extension doping is d
Publikováno v:
2021 China Semiconductor Technology International Conference (CSTIC).
Gate-grounded NMOS (GGNMOS) is one of the most used devices for electrostatic discharge (ESD). During the technology development, it was found that FinFET GGNMOS suffers from DC parameter variation problems. We try to explain the DC parameter variati
Publikováno v:
2019 China Semiconductor Technology International Conference (CSTIC).
In this work, a novel ultra high-voltage LDMOS device structure design is presented by multiple local RESURF enhancement technology to achieve breakdown voltage up to 500–700V as well as low on-state resistance. This innovative LDMOS structure is r
Publikováno v:
2019 China Semiconductor Technology International Conference (CSTIC).
Flicker Noise is the most important noise source for silicon CMOS, and it is very crucial for RF applications.In this report, we are able to simulate flicker noise by physical trap-detrap model with Sentaurus software, which computes the noise source
Autor:
XueJie Shi, TzuChiang Yu, Hao Sun, Ling Tang, Byunghak Lee, Miao Liao, Yongsheng Yang, Guiying Ma
Publikováno v:
2018 China Semiconductor Technology International Conference (CSTIC).
LDMOS (Laterally Diffused Metal Oxide Semiconductor) applications get extensively in high voltage and smart power management. However, high operational drain voltage makes LDMOS devices highly vulnerable to the damage caused by HCI (hot-carrier injec
Autor:
Qi Chen, Yongsheng Yang, Feilong Zhang, Guang Chen, Tony Li, Yuhua Cheng, Fei Lu, Tianshen Tang, Albert Wang, Xuejie Shi, Chenkun Wang, Li Hongwei, Danniel Feng, Cheng Li
Publikováno v:
2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
This paper reports characterization and analysis of diode string electrostatic discharging (ESD) protection structures fabricated in a foundry 28nm CMOS technology. Comprehensive measurements were conducted using very-fast transmission line pulse (VF
Autor:
QingChun Jason Zhang, Lei Fang, Shaofeng Yu, Hong Wu, JiaJia Jeremy Tao, Tao Allen Yang, Siyuan Frank Yang, Byung-Hak Lee, Yu Kellin Ding, XueJie Shi, Zicheng Pan, Yuejiao Pu
Publikováno v:
ECS Transactions. 60:9-14
In this paper, a practice of design of experiments and data analysis for 28nm technology NMOS devices was introduced. Integrated-Optimum Optimal Design design with I-optimality method criterion was used for 5 input variables with 3 levels for each de