Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Xuefan Jin"'
Publikováno v:
IEEE Access, Vol 6, Pp 59761-59767 (2018)
This paper describes a voltage-mode transmitter that stacks independent non-return-tozero (NRZ) and four-level pulse amplitude modulation (PAM4) drivers for dual channels. The stacked structure can improve the transmitter's power efficiency owing to
Externí odkaz:
https://doaj.org/article/69f03768fdf748dfa78a54586a23cf1d
Autor:
Dongsuk Kang, Jae-Woo Park, Injae Park, Min-Su Park, Xuefan Jin, Kyu-Dong Hwang, Dae-Han Kwon, Jung-Hoon Chun
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:3083-3093
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::789b438da2a3a5059e7c0e6cfabb547a
https://doi.org/10.1109/jssc.2022.3170439
https://doi.org/10.1109/jssc.2022.3170439
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:2724-2733
A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ff9723c90fb5efabdb13bcc007259b1
https://doi.org/10.1109/jssc.2020.3005806
https://doi.org/10.1109/jssc.2020.3005806
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 19:292-299
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cdc0debdfdb535df0646424f161f478
https://doi.org/10.5573/jsts.2019.19.3.292
https://doi.org/10.5573/jsts.2019.19.3.292
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2994-3003
This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::048435f362449b8dcb3565871bbe3370
https://doi.org/10.1109/jssc.2018.2856243
https://doi.org/10.1109/jssc.2018.2856243
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26:522-530
A 12.5-Gb/s complete near-ground transceiver is demonstrated. The output stage of the transmitter (TX) employs 2-tap finite-impulse response equalization (EQ) and also performs ac-coupled EQ for an additional EQ. A continuous-time linear equalizer (C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a21fbe84631cd1469294366c88d8cbc
https://doi.org/10.1109/tvlsi.2017.2773642
https://doi.org/10.1109/tvlsi.2017.2773642
Publikováno v:
IEEE Access, Vol 6, Pp 59761-59767 (2018)
This paper describes a voltage-mode transmitter that stacks independent non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM4) drivers for dual channels. The stacked structure can improve the transmitter’s power efficiency owing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::136b636decf4db51b254c1b7a8d80b0d
https://doi.org/10.1109/access.2018.2874630
https://doi.org/10.1109/access.2018.2874630
Publikováno v:
A-SSCC
A 4-GHz sub-harmonically injection-locked phase locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve a low phase noise. The phase noise of the proposed ILP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d345fe870d5f111699695cacd4ba2139
https://doi.org/10.1109/a-sscc47793.2019.9056966
https://doi.org/10.1109/a-sscc47793.2019.9056966
Publikováno v:
A-SSCC
This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e96adbeeb6feaab940d583594a016657
https://doi.org/10.5573/jsts.2016.16.4.387
https://doi.org/10.5573/jsts.2016.16.4.387
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 15:594-600
A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d316645daab84c2f172c83fdebcaa880
https://doi.org/10.5573/jsts.2015.15.6.594
https://doi.org/10.5573/jsts.2015.15.6.594