Zobrazeno 1 - 10
of 52
pro vyhledávání: '"Xavier Garros"'
Autor:
A. Krakovinsky, Louis Gerrer, R. Modica, Gerard Ghibaudo, Jérôme Biscarrat, J. Cluzel, William Vandendaele, Marie-Anne Jaud, Gaudenzio Meneghesso, F. Gaillard, Steve W. Martin, Xavier Garros, A. G. Viey, R. Gwoziecki, Marc Plissonnier, Ferdinando Iucolano, Matteo Meneghini
Publikováno v:
IEEE Transactions on Electron Devices. 68:2017-2024
In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI t
Autor:
Lauriane Contamin, Mikael Casse, Xavier Garros, Fred Gaillard, Maud Vinet, Philippe Galy, Andre Juge, Emmanuel Vincent, Silvano de Franceschi, Tristan Meunier
Publikováno v:
2022 IEEE International Reliability Physics Symposium (IRPS).
Autor:
Roméo KOM KAMMEUGNE, Charles Leroux, Tadeu Mota Frutuoso, Jacques Cluzel, Laura Vauche, Romain Gwoziecki, Xavier Garros, Matthew Charles, Edwige Bano, Gérard Ghibaudo
Publikováno v:
SSRN Electronic Journal.
Autor:
Benoit Sklenard, Bastien Giraud, Sebastien Thuries, Mikael Casse, Joris Lacord, Cm. Ribotta, V. Lapras, P. Acosta-Alba, O. Billoint, M. Mouhdach, N. Rambal, Pascal Besson, Francois Andrieu, Perrine Batude, Didier Lattard, Laurent Brunet, Gilles Sicard, Xavier Garros, Christoforos G. Theodorou, L. Brevard, Maud Vinet, V. Mazzocchi, P. Sideris, M. Ribotta, Claire Fenouillet-Beranger, F. Ponthenier, Pascal Vivet, Sebastien Kerdiles, G. Cibrario, J.M. Hartmann, Frank Fournel, Bernard Previtali, Frédéric Mazen, Claude Tabone
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC)
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
2021 IEEE International Interconnect Technology Conference (IITC), Jul 2021, Kyoto, France. pp.1-1, ⟨10.1109/IITC51362.2021.9537356⟩
The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a896dcadaa6b8a425398da1a162204f
https://hal.archives-ouvertes.fr/hal-03434018
https://hal.archives-ouvertes.fr/hal-03434018
Autor:
Xavier Garros, Jose Lugo-Alvarez, Laurent Brunet, Perrine Batude, Christoforos G. Theodorou, P. Sideris, Philippe Ferrari, C. Fenouille-Beranger, T. Mota Frutuoso, F. Gaillard
Publikováno v:
IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
IEEE Transactions on Electron Devices, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
IEEE Transactions on Electron Devices, 2021, pp.1-6. ⟨10.1109/TED.2021.3080669⟩
RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GH
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::623ed3653c9c7d850202b6198472443c
https://hal.archives-ouvertes.fr/hal-03260955
https://hal.archives-ouvertes.fr/hal-03260955
Autor:
A. Krakovinsky, Jérôme Biscarrat, R. Gwoziecki, Ferdinando Iucolano, Matteo Meneghini, Xavier Garros, F. Gaillard, Steve W. Martin, R. Modica, Marie-Anne Jaud, William Vandendaele, A. G. Viey, Marc Plissonnier, Gaudenzio Meneghesso, Louis Gerrer, J. Cluzel, G. Ghibaudo
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
In this paper, threshold voltage V TH instabilities under positive gate voltage stress (V GStress ) are thoroughly investigated on GaN-on-Si Enhancement-mode MOS-channel HEMTs. An analysis of pBTI transients performed at several V GStress and tempera
Publikováno v:
IEEE Electron Device Letters
IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2020, 41 (10), pp.1460-1463. ⟨10.1109/LED.2020.3016383⟩
IEEE Electron Device Letters, 2020, 41 (10), pp.1460-1463. ⟨10.1109/LED.2020.3016383⟩
IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers, 2020, 41 (10), pp.1460-1463. ⟨10.1109/LED.2020.3016383⟩
IEEE Electron Device Letters, 2020, 41 (10), pp.1460-1463. ⟨10.1109/LED.2020.3016383⟩
A novel technique is presented for a direct evaluation of oxide breakdown under AC stress at high frequencies up to 500MHz. It relies on a RF setup, which combines a high speed pulse generator, transition converters and $50\Omega $ termination probes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0bd7555ff735544fe842ce6f1afbb5b3
https://hal.archives-ouvertes.fr/hal-02961016
https://hal.archives-ouvertes.fr/hal-02961016
Autor:
Benoit Sklenard, Joris Lacord, D. Lattard, R. Nait Youcef, Xavier Garros, A. Tataridou, Francois Andrieu, Claire Fenouillet-Beranger, F. Balestra, Sylvain Barraud, Perrine Batude, G. Audoit, Mikael Casse, D. Bosch, J. Lugo, Christoforos G. Theodorou, Laurent Brunet, J.-P. Colinge, J. Cluzel, F. Allain, C. Vizioz, J.M. Hartmann
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.126-127, ⟨10.1109/VLSI-TSA48913.2020.9203690⟩
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.126-127, ⟨10.1109/VLSI-TSA48913.2020.9203690⟩
We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::22aa19246805ca5305905064aa067feb
https://hal.science/hal-02969748/file/vlsi_tsa_BOSCH_HAL.pdf
https://hal.science/hal-02969748/file/vlsi_tsa_BOSCH_HAL.pdf
Autor:
Charles Leroux, Florian Domengie, Blend Mohamad, Carlos Suarez Segovia, Xavier Garros, P. Blaise, G. Reimbold, Gerard Ghibaudo, Pushpendra Kumar
Publikováno v:
ECS Transactions. 80:237-245
Autor:
Xavier Federspiel, Gilles Reimbold, Amer Diab, Xavier Garros, Mustapha Rafik, Emmanuel Vincent
Publikováno v:
Microelectronic Engineering. 178:21-25
In this paper, we studied the influence of adding gate impedance (Rg) on the breakdown reliability of 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) transistors. We have shown that Rg plays a crucial role by affecting the hardness of breakdown (HBD