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A Comprehensive Review of Applications of Don't Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Autor: Sanjoy Mitra, Debaprasad Das

Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. Many low-power methodologies are found in the technical literature to address this issue of test mode high power consumption and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=od______2659::1b231741eb2fd554d52a1eaad3db6016
https://zenodo.org/record/4057887

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Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch

Autor: Seiji Kajihara, Michael A. Kochte, Xiaoqing Wen, Stefan Holst, K. Asada, Jun Qian, Hans-Joachim Wunderlich, Eric Schneider, Kohei Miyase

Publikováno v: ATS

IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ab5da88a2b4aa6fe340eab91b25f7e0a
https://kyutech.repo.nii.ac.jp/records/6375

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Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures

Autor: Dandan Shen, Wei Wang, Huaguo Liang, Xin Yi, Xiaoqing Wen, Tian Chen

Publikováno v: IEICE Transactions on Information and Systems. :2672-2681

Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::65b62496b6bae2160dbfb7b73de6e945
https://doi.org/10.1587/transinf.2015edp7289

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Akademický článek

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Akademický článek

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Transition Analysis for Power Reduction in SoC

Autor: A. Balasubramaniyan, B. Ganesh, P. Selvakumar, S. Saravanan, R. Silambamuthan, R. Pannerselvam

Publikováno v: Procedia Engineering. 38:655-660

Size and complexity have been major issues for System-on-a-Chip (SoC) testing. Transition analysis plays a significant role in power consideration of SoC testing. Transition is directly propositional to the power. This paper is based on finding trans

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::22089c65314b2a03b92a7f0b905f831b

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Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing

Autor: Seiji Kajihara, Yuta Yamato, Xiaoqing Wen, Hideaki Ito, Takashi Aikyo, Kenji Noda, Kohei Miyase, Kazumi Hatayama, Hiroshi Furukawa

Publikováno v: IEICE Transactions on Information and Systems. (6):1216-1226

Test data modification based on test relaxation and X-filling is the preferred approach for reducing excessive IR-drop in at-speed scan testing to avoid test-induced yield loss. However, none of the existing test relaxation methods can control the di

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::69f4ed76a8e29d9e8886f84a59cc9c73
https://kyutech.repo.nii.ac.jp/records/6322

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A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing

Autor: Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato

Publikováno v: IEICE TRANSACTIONS on Information and Systems. (4):833-840

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing. However, the ability of previous X-filling methods to reduce launch switching activity may be unsatisfactory, due to low effect (insuffici

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f43567b1553dd3135fa8ed347810167c
http://hdl.handle.net/10061/11104

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