Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Wooseung Yang"'
Publikováno v:
Korean Chemical Engineering Research. 50:177-181
Dye-sensitized solar cells(DSSCs) based on TiO2 film photo anode incorporated with different amount of grapheme nanosheet(GNS) are fabricated and their photovoltaic performance are investigated. The TiO2-GNS compos- ite electrode has been prepared by
Publikováno v:
Organic Electronics. 13:273-282
Two new small molecules, 5,5-bis(2-triphenylamino-3-decylthiophen-2-yl)-2,2-bithiazole ( M1 ) and 2,5-bis(2-triphenylamino-3-decylthiophen-2-yl)thiazolo[5,4-d]thiazole ( M2 ) based on an electron-donor triphenylamine unit and electron-acceptor thioph
Publikováno v:
Synthetic Metals. 161:1582-1589
A new alternating donor–acceptor conjugated copolymer, poly{(2,5-bis(3-decylthiophen-2-yl)thiazolo[5,4-d]thiazole-5,5′-diyl)-alt-(2,6-[(1,5-didecyloxy)naphthalene])} (PNTzTz) based on thiazolothiazole and didecyloxynaphthalene units was synthesiz
Autor:
Wooseung Yang, Chong-Min Kyung
Publikováno v:
Journal of Circuits, Systems and Computers. 14:137-157
FPGA-based emulation, which is now widely used in the design and verification of System-on-a-Chip (SoC), is applicable only when the RTL design for the whole system is available, thus resulting in a long design turn-around time. In this paper, we pre
Publikováno v:
Chem. Commun.. 48:573-575
Two new small molecules with a rigid planar naphtho[1,2-b:5,6-b']dithiophene (NDT) unit were designed and synthesized. Solution processed bulk-hetereojunction organic solar cells based on blends of the small molecules and [6,6]-phenyl-C(71)-butyric a
Publikováno v:
ChemInform. 43
Organic solar cells based on compound (IIIb) exhibit promising photovoltaic device performance with a maximum power conversion efficiency up to 2.20% under the illumination of AM 1.5G, 100 mW cm-2.
Publikováno v:
Essential Issues in SOC Design ISBN: 9781402053511
Verification of System-On-a-Chip (SoC) poses us a serious challenge as it involves not only high chip complexity but also hardware/software co-verification along with short design time-to-market. Traditional IC design verification technologies based
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08ce3b22ba95f40ff2751335d708445d
https://doi.org/10.1007/1-4020-5352-5_7
https://doi.org/10.1007/1-4020-5352-5_7
Automatic generation of software/hardware co-emulation interface for transaction-level communication
Autor:
Ki-Yong Aim, Young-Su Kwon, Wooseung Yang, Chong-Min Kyung, Heejun Shim, Young-Jin Kim, Ando Ki
Publikováno v:
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..
This paper presents a methodology for generating interface of a co-emulation system where processor and emulator execute testbench and design unit, respectively while interacting with each other. To reduce the communication time between the processor
Publikováno v:
ASP-DAC
This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and
Publikováno v:
Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.
In this paper we present a new RTL debugging methodology in FPGA-based verification platform. This method provides internal node probing in the co-simulation environment. Full observability is guaranteed using 32-bit scan module generated automatical