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Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:2876-2889
This paper presents a new time-based pipelined analog-to-digital converter (ADC) with multiplying-DAC (MDAC) stages capable of robust $2 \times $ residue amplification by subtracting two pulse widths. First, the input voltage is converted into two ti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe052994e9d43d6585844f25564e0264
https://doi.org/10.1109/tcsi.2021.3079338
https://doi.org/10.1109/tcsi.2021.3079338
