Zobrazeno 1 - 10
of 82
pro vyhledávání: '"Woorham Bae"'
Autor:
Woorham Bae
Publikováno v:
IEEE Access, Vol 10, Pp 80680-80694 (2022)
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a
Externí odkaz:
https://doaj.org/article/88ed65f1205e40dea855688c9432fe01
Publikováno v:
IEEE Access, Vol 7, Pp 38035-38043 (2019)
This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage
Externí odkaz:
https://doaj.org/article/0864df041941476f9510a96fbe7c11be
Autor:
Woorham Bae
Publikováno v:
PeerJ Computer Science, Vol 7, p e420 (2021)
Due to the explosive increase of digital data creation, demand on advancement of computing capability is ever increasing. However, the legacy approaches that we have used for continuous improvement of three elements of computer (process, memory, and
Externí odkaz:
https://doaj.org/article/c38a5afafe1c4af384e410f2915d4273
Autor:
Woorham Bae, Kyung Jean Yoon
Publikováno v:
Advanced Intelligent Systems, Vol 2, Iss 5, Pp n/a-n/a (2020)
Herein, a robust programmable stochastic weight generation method for a memristive neural network is proposed. There have been few prior algorithm suggestions for crossbar neural network‐based stochastic learning; however, there has not been much a
Externí odkaz:
https://doaj.org/article/6604d22199354578b814e3fda60a1a36
Autor:
Woorham Bae
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 9, Iss 3, p 26 (2019)
Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog cir
Externí odkaz:
https://doaj.org/article/65ccd2361ba245bd8c3f42d7caa3d46e
Publikováno v:
Sensors, Vol 17, Iss 9, p 1962 (2017)
The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy elect
Externí odkaz:
https://doaj.org/article/1b17f69b994f4da488677f689c9ef5a3
Publikováno v:
IEEE Solid-State Circuits Letters. 6:41-44
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d99f77a8f2e2219c1c8d61b1e42f69a
https://doi.org/10.1109/lssc.2023.3242902
https://doi.org/10.1109/lssc.2023.3242902
Autor:
Vladimir Milovanovic, Colin Schmidt, Krste Asanovic, Zhongkai Wang, Brian Richards, Sean Huang, Borivoje Nikolic, Elad Alon, Woorham Bae, Eric Chang, Albert Ou, Anita M. Flynn, John Wright
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:140-152
This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator-based design methodology, which enables the integration of open-source and proj
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7035a1579f164861334ed01940fd752
https://doi.org/10.1109/jssc.2021.3118046
https://doi.org/10.1109/jssc.2021.3118046
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:1012-1022
LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC ins
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::213bdd506616026d064a0979b745eda6
https://doi.org/10.1109/tcsi.2020.3046524
https://doi.org/10.1109/tcsi.2020.3046524
