Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Woo-Yol Lee"'
Publikováno v:
ISCAS
This paper proposes a pipeline ADC consisting of a first stage SAR ADC and a second stage Flash ADC. This ADC has a 10-bit resolution at 0.9 V power supply voltage and operates at 400 MS/s. The first stage SAR ADC is 6bit resolution, operates in an a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e155f3e8daf5bfda7eba526b4e9edfb
https://doi.org/10.1109/iscas51556.2021.9401263
https://doi.org/10.1109/iscas51556.2021.9401263
Autor:
Jong-Kee Kwon, Young Kyun Cho, Kuk-Tae Hong, Young-Deuk Jeon, Kwi-Dong Kim, Jae-Won Nam, Woo-Yol Lee
Publikováno v:
CICC
This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbf509455b29e465fde7693d814d69c8
https://doi.org/10.1109/cicc.2010.5617457
https://doi.org/10.1109/cicc.2010.5617457
Autor:
Young-Deuk Jeon, Seung-Chul Lee, Jeong-Woong Moon, Jong-Kee Kwon, Jongdae Kim, Woo-Yol Lee, Kwi-Dong Kim
Publikováno v:
ISSCC
A 10b 205MS/S 1mm2 ADC for flat-panel display applications is implemented in a 90nm CMOS process. The ADC with an LDO regulator achieves a 53dB PSRR for a 100MHz noise tone and a 55.2dB SNDR for a 30MHz 1Vpp single-ended input at 205MS/S. The core AD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14a56222924fe903d206842713e6520b
https://doi.org/10.1109/isscc.2007.373492
https://doi.org/10.1109/isscc.2007.373492
Autor:
Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon
Publikováno v:
2010 IEEE Custom Integrated Circuits Conference (CICC); 2010, p1-4, 4p