Zobrazeno 1 - 10
of 17
pro vyhledávání: '"WonChul Do"'
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Eoin O'Toole, Jose Luis Silva, Filipe Cardoso, Jose Silva, Luis Alves, Marcio Souto, Nuno Delduque, Anibal Coelho, Jose Miguel Silva, WonChul Do, JinYoung Khim
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
MinKeon Lee, Dave Hiner, WonChul Do, Michael G. Kelly, GamHan Yong, MinSu Jeong, JiHun Lee, JinYoung Khim, JongHyun Jeon, Eun-Sook Sohn, DongHoon Han
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipa
Autor:
SeHwan Hong, David Jon Hiner, EunYoung Lee, JiYeon Ryu, JaeYoon Kim, KyeRyung Kim, JiHun Lee, WonChul Do, JinYoung Khim, Ji Hyun Kim
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, c
Autor:
Ji Hun Lee, JaeYoon Kim, EunYoung Lee, KyeRyung Kim, WonChul Do, SeHwan Hong, MinKeon Lee, David Jon Hiner, JuHong Shin
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
In this work, a hybrid 3D package combining a redistribution layer (RDL) and laminate substrate layer for ultra-thin and high-bandwidth mobile applications are discussed and demonstrated. The motivation behind this hybrid 3D package structure was lev
Autor:
GyuIck Jung, SooHyun Kim, HoDol Yoo, WonChul Do, TaeKyeong Hwang, WonMyoung Ki, JaeHun Bae, InSu Mok, SeungMan Ryu
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process. The redistribution
Autor:
KiYeul Yang, JunHwan Park, WonChul Do, SangHyoun Lee, JinKun Yoo, SeokHun Yun, JinYoung Khim, MinJae Yi, JiHun Yi, EunTaek Jeong, SeungNam Son, DongHyun Khim
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Fan-Out Wafer-Level Interposer Package-on-Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor and heterogeneous integration for multi-functions. In addition, it can be a
Autor:
Michael G. Kelly, SangHyoun Lee, Ron Huemoeller, JinYoung Khim, WonChul Do, YoungDo Kweon, KwangSeok Oh, HyunHye Jung, MiKyeong Choi, DongSu Ryu, KyungRok Park
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
The capability and diversity of high-performance microprocessors is increasing with each process technology generation to meet increasing application demands. The cooling designs for these chips must deal with larger temperature gradients across the
Autor:
InSu Mok, Curtis Zwenger, Moh Kolbehdari, IlBok Lee, Alex Copia, WonChul Do, Kang-Wook Lee, Wongeol Lee, Suresh Jayaraman, WonMyoung Ki
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
Fan-out wafer level packaging (FOWLP) is one of the latest technologies to meet the requirements of high performance and thin form-factor, especially for mobile application processors. To achieve a simple path way and thinner package form, many outso