High-Temperature Characterizations of a Half-Bridge Wire-Bondless SiC MOSFET Module

Autor: Yue Chen, Guangyin Lei, Guo-Quan Lu, Yun-Hui Mei

Publikováno v: IEEE Journal of the Electron Devices Society, Vol 9, Pp 966-971 (2021)

SiC MOSFET allows higher temperature capability with higher switching efficiency than that of conventional Si devices, due to its superior electrical and thermal properties. Nevertheless, there are few reports on the systematic characterization of th

Externí odkaz: https://doaj.org/article/1f7551f9872045d480a79101136b5ab4

High-Temperature Characterizations of a Half-Bridge Wire-Bondless SiC MOSFET Module

Autor: Guangyin Lei, Yue Chen, Guo-Quan Lu, Yunhui Mei

Publikováno v: IEEE Journal of the Electron Devices Society, Vol 9, Pp 966-971 (2021)

SiC MOSFET allows higher temperature capability with higher switching efficiency than that of conventional Si devices, due to its superior electrical and thermal properties. Nevertheless, there are few reports on the systematic characterization of th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::dcafad9c4d879805174571477851c7dd
https://ieeexplore.ieee.org/document/9568652/

Sinterconnects: All-Copper Top-Side Interconnects Based on Copper Sinter Paste for Power Module Packaging

Autor: Muhammad-Hassan Malik, Ali Roshanghias, Timothy A. Polom, Jochen Bardong, Alfred Binder, Perla Malago, Michael Ortner, Dominik Holzmann, Jaroslaw Kaczynski, Christina Hirschl

Publikováno v: Energies
Energies, Vol 14, Iss 2176, p 2176 (2021)
Volume 14
Issue 8

Copper sinter paste has been recently established as a robust die-attach material for high -power electronic packaging. This paper proposes and studies the implementation of copper sinter paste materials to create top-side interconnects, which can su

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3cce3473efac1573762d5d98b2c1fd6e
https://doi.org/10.3390/en14082176

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Solderless Leadframe Assisted Wafer-Level Packaging Technology for Power Electronics

Autor: Julie Widiez, Bastien Letowski, Pierre Perreau, Jean-Christophe Crebier, Perceval Coudrain, Kremena Vladimirova, Gregory Enyedi, Nicolas Rouger

Publikováno v: 2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, France. pp.1251-1257, ⟨10.1109/ECTC.2018.00193⟩

International audience; This paper presents a wafer-level pre-packagingtechnology for power devices. The concept consists in theimplementation of a thick 3D patterned copper leadframeensuring the interconnections of the power devices amongthem or wit

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::02f98f81ae7cfcdd1209324739ad54c4
https://cea.hal.science/cea-02185324