Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Winston, A.J."'
Autor:
Di Lemma, F.G., Jue, J.F., Winston, A.J., Pu, X., Anderson, S., Keiser, D.D., Giglio, J.J., Cole, J.I.
Publikováno v:
In Journal of Nuclear Materials June 2022 564
Akademický článek
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Publikováno v:
The International Journal of Electrical Engineering & Education. 37:108-117
Cet article examine le developpement d'un cursus en ingenierie numerique qui integre intimement les outils EDA et le materiel d'enseignement par multimedia dans le syllabus. Il decrit le logiciel qui a ete integre y compris les outils pour la saisie
Publikováno v:
Microelectronics Journal. 24:217-223
The design and test results of an 8 × 8 bit high-speed two's complement multiplier fabricated in a 1·5 μm n-well CMOS process are presented in this paper. The design is based on the well known modified Booth's algorithm which gives high speed at r
Publikováno v:
The International Journal of Electrical Engineering & Education. 28:271-277
Teaching VSLI design using ChipWise ChipWise is a design system for VLSI circuits developed at the University of Kent, based on tools which originated at several academic institutions and tools obtained from industry. From 1st August, 1990, ChipWise
Autor:
Winston A.J. Waller, Les T. Walczowski
Publikováno v:
ICECS
A World Wide Web (WWW) based client/server system has been developed which uses Java servlet technology. The system allows a server-side, process-independent layout generator servlet to generate active messages, which create design rule correct geome
Publikováno v:
ICECS
A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, a design rule correct layout is generated. T
Publikováno v:
2nd International Conference on ASIC.
Bipolar op-amp IC modules with a simple circuit structure are difficult to design for a wide range of design specifications, due to strong correlations between transistor parameters. As a result, bipolar op-amps are commonly designed resorting to com
Publikováno v:
VLSI Design
Differential Split-Level (DSL) CMOS logic offers large speed improvement in CMOS circuit techniques. In this paper, the problem of testing DSL circuits is addressed for the first time to the best of our knowledge. The behaviour of DSL circuits under
Publikováno v:
1991., IEEE International Sympoisum on Circuits and Systems.
The authors present a method for automatically calculating the size of the transistors and passive components in a CMOS op-amp given the specification and loading of the op-amp. The method is similar to that used in the OASYS program in that it uses