Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Winson Lin"'
Autor:
Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Jae Wook Kim, Chuen-huei Adam Chou, Kee Hian Tan, Kun-Yung Ken Chang, Adebabay M. Bekele, Yohan Frans, H. Ahn, Ilias Chlis, Yipeng Wang, Arianne Roldan, David Mahashin, H.-W. Hung, Stanley Chen, Lei Zhou, Declan Carey, Hongtao Zhang, Ronan Casey, Jay Im, Ying Cao, Winson Lin, Kevin Zheng
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:7-18
A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inve
Autor:
Yipeng Wang, Junho Cho, Eugene Ho, Ma Shaojun, Asma Laraba, Yohan Frans, Daniel Wu, Kee Hian Tan, Wenfeng Zhang, Chi Fung Poon, Ying Cao, Parag Upadhyaya, Winson Lin
Publikováno v:
VLSI Circuits
This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12
Autor:
Nakul Narang, Siok Wei Lim, Bruce Xu, Kee Hian Tan, Toan Pham, Wenfeng Zhang, Junho Cho, Geoff Zhang, Chi Fung Poon, Hongtao Zhang, Parag Upadhyaya, Winson Lin, Jin Namkoong, Yohan Frans, Ken Chang, Arianne Roldan
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:18-28
The design of a dual-mode, 19–58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5–29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear eq
Autor:
Yohan Frans, Hongtao Zhang, David Mahashin, Winson Lin, Yipeng Wang, Jay Im, Stanley Chen, Ken Chang, Adam Chou, Kevin Zheng, Hao-Wei Hung, Arianne Roldan, Ying Cao, Lei Zhou, Declan Carey, Ilias Chlis, Hong Ahn, Jae Wook Kim, Kee Hian Tan, Ronan Casey, Ade Bekele
Publikováno v:
ISSCC
Interest in 112Gb/s wireline transceivers targeting data center and communication applications has rapidly increased. PAM-4 signaling remains the dominant choice of modulation scheme due to its superior spectral efficiency [1-2]. This paper reports a
Autor:
Jay Im, Ken Chang, Yohan Frans, Neto Pedro W, Ronan Casey, Kay Hearne, Declan Carey, Bruce Xu, Marc Erett, Vikas Sooden, Winson Lin, Wenfeng Zhang, Kevin Geary, Thomas Mallard, James Hudner, Parag Upadhyaya, Mark Smyth
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:1783-1797
This paper presents a flexible-reach 0.5–16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a
Autor:
Bruce Xu, Ronan Casey, Haibing Zhao, Mayank Raj, James Hudner, Ken Chang, Kee Hian Tan, Hongtao Zhang, Ted Lee, Neto Pedro W, Winson Lin, Declan Carey, Nakul Narang, Marc Erett, Ping-Chuan Chiang, Hongyuan Zhao, Arianne Roldan, Kevin Geary, Yohan Frans
Publikováno v:
CICC
A multi-lane short-reach wireline transceiver is implemented in 16nm FinFET. Taking advantage of a low-loss channel with minimum reflections, 56Gbps NRZ differential signaling is employed, using only a continuous time linear equalizer (CTLE) in the r
Autor:
David Mahashin, Tim Cronin, Adebabay M. Bekele, Stanley Chen, Hongyuan Zhao, Ian Zhuang, Parag Upadhyaya, Adam Chou, Winson Lin, Kee Hian Tan, Dave Freitas, Lei Zhou, Kok Lim Chan, Yohan Frans, Jay Im, Ken Chang, Didem Turker
Publikováno v:
VLSI Circuits
A 28Gb/s NRZ wireline transceiver is implemented in 7nm FinFET. A transformer-based LC-PLL sends a single-phase differential clock to the voltage-mode transmitter and the receiver. Local multi-phase clocks are generated in each TX/RX lane to support
Autor:
Nakul Narang, Kee Hian Tan, Geoff Zhang, Siok Wei Lim, Chi Fung Poon, Toan Pham, Yohan Frans, Junho Cho, Jin Namkoong, Bruce Xu, Arianne Roldan, Ken Chang, Wenfeng Zhang, Hongtao Zhang, Winson Lin, Parag Upadhyaya
Publikováno v:
ISSCC
Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without significant increase in cost or power per bit. In order to mitigate the cost of infrastructure upgrad
Autor:
Hiva Hedayati, Scott McLeod, Jin Namkoong, Mohamed N. Elzeftawi, Jay Im, Ken Chang, Yohan Frans, Winson Lin, Parag Upadhyaya
Publikováno v:
ISSCC
Due to increasing bandwidth demand in data centers and telecommunication infrastructures, the maximum data-rate of wireline transceivers is projected to double from 32Gb/s to 64Gb/s while keeping the same power envelope. This paper presents the desig