Zobrazeno 1 - 5
of 5
pro vyhledávání: '"William W. Bereza"'
Autor:
C. Berndt, W. Fergusson, William W. Bereza, Albert Vareljian, Rakesh H. Patel, Mohsen Moussavi
Publikováno v:
CICC
A simple high-performance nonlinear digital PLL is fabricated in 90 nm CMOS with operating range of 0.5 to 3.25 GHz and 1.24 ps jitter. New insights into the PLL behavior are discussed. The classical “20Log” in-band phase noise tracking does not
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd85feb398adda86e3de1f0ca89d7311
https://doi.org/10.1109/cicc.2009.5280834
https://doi.org/10.1109/cicc.2009.5280834
Publikováno v:
CICC
The modeling and simulation of an all-digital PLL is presented. Verilog-A, owing to its flexibility, is used to create both behavioral and gate-level models used in system-level and circuit-based simulation. The methodology presented allows us to sim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::986d63bb5b5c310af61fa204c0349382
https://doi.org/10.1109/cicc.2007.4405863
https://doi.org/10.1109/cicc.2007.4405863
Autor:
William W. Bereza, Rakesh H. Patel
Publikováno v:
CICC
A 275mW at 6.375Gbps High Speed Serial Interface developed in TSMC?s 90nm triple-gate oxide CMOS process and the customized methodology applied to develop and integrate high-speed mixed-signal IPs into FPGA platforms will be presented. The risk reduc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66f95273f83322a438a2382c12647f4d
https://doi.org/10.1109/cicc.2006.320979
https://doi.org/10.1109/cicc.2006.320979
Publikováno v:
CICC
This paper examines two popular bang-bang CDR architectures: one is with a conventional RC loop filter which often involves a 3rd order loop design and the other is with a separate proportional path which involves a straightforward 2nd order loop des
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::579d63bb08206a602ea13aa18650c913
https://doi.org/10.1109/cicc.2005.1568669
https://doi.org/10.1109/cicc.2005.1568669
Publikováno v:
CICC
This paper embodies a methodology used to create high-speed transceiver behavior models employed within a signal integrity-based link simulation platform. This tool includes routines for the optimization of transmitter pre-emphasis and equalization.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a72423bc4fa0191b831c84a94efb077
https://doi.org/10.1109/cicc.2005.1568770
https://doi.org/10.1109/cicc.2005.1568770