Zobrazeno 1 - 10
of 40
pro vyhledávání: '"William V. Huott"'
Autor:
Peilin Song, Uma Srinivasan, Phong T. Tran, Franco Stellari, Dave Albert, William V. Huott, Chad Allen Adams, Pete Freiburger
Publikováno v:
NATW
This paper is a case study of diagnostic techniques used to debug a particularly difficult fail in a multi-port register file memory that appeared to increase its minimum functional voltage (VMIN) over time. Some of the debug techniques used involved
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4726ef32d67179c48b6397c30f92a608
https://doi.org/10.1109/natw.2019.8758709
https://doi.org/10.1109/natw.2019.8758709
Autor:
Howard H. Smith, Antonio R. Pelella, Patrick J. Meaney, Pradip Patel, D. Malone, G. Gerwig, S. Carey, William V. Huott, James D. Warnock, David L. Rude, Thomas Strach, Frank Malgioglio, Huajun Wen, Daniel Rodko, Yuen Chan, Paul A. Bunce, Jose L. Neves, Yiu-Hing Chan, John Davis
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:151-163
This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e540a64872963d1dea4d5479786ea8c0
https://doi.org/10.1109/jssc.2011.2169308
https://doi.org/10.1109/jssc.2011.2169308
Autor:
William V. Huott, Steven E. Steen, Jeffrey A. Kash, James C. Tsang, Stas Polonsky, M.K. Mc Manus, Daniel R. Knebel
Publikováno v:
Microelectronics Reliability. 40:1353-1358
Normal operation of complementary metal-oxide semiconductor (CMOS) devices entails the emission of picosecond pulses of light, which can be used to diagnose circuit problems. The pulses that are observed from submicron sized field effect transistors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c5862ed95a5f8e0b212bd4ddc2b81ad
https://doi.org/10.1016/s0026-2714(00)00137-2
https://doi.org/10.1016/s0026-2714(00)00137-2
Autor:
Mary P. Kusko, T.G. Foote, Bryan J. Robbins, William V. Huott, Timothy J. Koprowski, D.E. Hoffman
Publikováno v:
IEEE Design & Test of Computers. 15:83-89
The design-for-test framework of the 500-MHz CMOS central processor uses specific tests to ensure the highest reliability of components within a system. Some of the same test patterns are applied in chip manufacturing and system-level tests.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d22e225dc7da4201e6d70f14b23b05d
https://doi.org/10.1109/54.706038
https://doi.org/10.1109/54.706038
Autor:
M. Mayo, Y.H. Chan, J. P. Eckhardt, Ching-Te Chuang, L. Sigal, Daniel R. Knebel, Brian W. Curran, James D. Warnock, Peng Wu, Peter J. Camporese, William V. Huott
Publikováno v:
IBM Journal of Research and Development. 41:489-503
This paper describes the circuit design techniques used for the IBM S/390® Parallel Enterprise Server G4 microprocessor to achieve operation up to 400 MHz. A judicious choice of process technology and concurrent top-down and bottom-up design approac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e19686b14860bbc642e19023f3eda7ac
https://doi.org/10.1147/rd.414.0489
https://doi.org/10.1147/rd.414.0489
Autor:
Timothy G. McNamara, T.J. Snethen, Timothy J. Koprowski, William V. Huott, S. V. Pateras, Dale Eugene Hoffman, Mary P. Kusko, Bryan J. Robbins
Publikováno v:
IBM Journal of Research and Development. 41:611-627
This paper describes the overall test methodology used in implementing the S/390® microprocessor and the associated L2 cache array in shared multiprocessor designs, the design-for-test implementations, and the test software used in creating the test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6892d288e9429b096c3d9517f24ff0c
https://doi.org/10.1147/rd.414.0611
https://doi.org/10.1147/rd.414.0611
Autor:
Gerard M. Salem, B. Truong, Y.-H. Chan, S. Carey, Huajun Wen, D. Malone, Guenter Mayer, Brian W. Curran, Donald W. Plass, Y.H. Chan, Pak-Kin Mak, William V. Huott, Frank Malgioglio, Thomas Strach, M. Mayo, Timothy J. Slegel, James D. Warnock
Publikováno v:
2011 IEEE International Conference on IC Design & Technology.
The IBM zEnterprise z196 processor chip is an energy efficient high-frequency, high-performance design that implements 4 processor cores optimized for maximum single-thread performance. Chip energy efficiency is improved by 25% compared to the previo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71261aab09d3e23517c976e9c8a623a4
https://doi.org/10.1109/icicdt.2011.5783229
https://doi.org/10.1109/icicdt.2011.5783229
Autor:
Brian W. Curran, Y.-H. Chan, S. Carey, Patrick J. Meaney, M. Mayo, L. Sigal, Guenter Mayer, Michael Fee, Lee Evan Eisen, Eric M. Schwarz, Pak-Kin Mak, D. Malone, Frank Malgioglio, Howard H. Smith, T. J. McPherson, Huajun Wen, Thomas Strach, Michael H. Wood, William V. Huott, M. J. Saccamango, James D. Warnock, S. Weitzel, Yuen H. Chan, David L. Rude, R. Averill, Donald W. Plass, Charles F. Webb
Publikováno v:
ISSCC
The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm des
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a548ff33e6ac1c480eb79f9a8031262
https://doi.org/10.1109/isscc.2011.5746223
https://doi.org/10.1109/isscc.2011.5746223
Autor:
Mary P. Kusko, Edward Michael Seymour, B. Walsh, Orazio P. Forlenza, Donato O. Forlenza, Timothy D. Taylor, James M. Crafts, Dennis R. Conti, William V. Huott, David C. Bogdan
Publikováno v:
ITC
The IBM Power 7™ 4 GHz, eight core microprocessor introduced several new challenges for the Power 7 test team: new pervasive test architecture, 8 asynchronous processor cores, DRAM integrated on the same die as processor and enhanced thermal test r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbf65da51ebe36eee4060cf2febb9171
https://doi.org/10.1109/test.2010.5699204
https://doi.org/10.1109/test.2010.5699204
Autor:
Donald W. Plass, S. Wu, R.L. Franch, S. Wilson, Robert M. Houle, Y.-H. Chan, Rajiv V. Joshi, Daniel Rodko, William V. Huott, Rouwaida Kanj, Pradip Patel
Publikováno v:
2008 IEEE Symposium on VLSI Circuits.
A hardware based, fully functional, stable 2.4 Mb L1 and L2 Cache compatible 6T embedded SRAM is demonstrated. Measured results show an operating range of -40degC to 120degC, speed of 6.5 GHz and 3.8 GHz for L1-Cache cells and L2-Cache cells, respect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd6607ed31dd610621ecba68687cc9e1
https://doi.org/10.1109/vlsic.2008.4586009
https://doi.org/10.1109/vlsic.2008.4586009