Zobrazeno 1 - 10
of 13
pro vyhledávání: '"William Robert Reohr"'
Autor:
William Robert Reohr, R. Freese, John W. Golz, Jente B. Kuang, Paul C. Parries, Gregory J. Fredeman, Jethro C. Law, Trong V. Luong, Pamela Wilcox, Hien Minh Le, Abraham Mathews, David Dick, Hillery C. Hunter, Erik A. Nelson, Subramanian S. Iyer, Toshiaki Kirihata, Gary Koch, A. Khargonekar, Hung C. Ngo, John E. Barth, Peter Juergen Klim
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:1216-1226
We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f68712ec5bfaf69d78fe5b66dec9430d
https://doi.org/10.1109/jssc.2009.2014207
https://doi.org/10.1109/jssc.2009.2014207
Publikováno v:
IEEE Micro. 28:47-56
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85abe0253db76a9799148ae7ec8e9c0d
https://doi.org/10.1109/mm.2008.93
https://doi.org/10.1109/mm.2008.93
Autor:
C. Tanner, K. Yanagisawa, Richard E. Matick, J. Griesemer, Hillery C. Hunter, Babar A. Khan, Paul C. Parries, Kim Hoki, John W. Golz, Subramanian S. Iyer, Gregory J. Fredeman, J. Harig, John E. Barth, R.P. Havreluk, T. Kirihata, Stanley E. Schuster, William Robert Reohr
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:86-95
As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3dc46e0324a6411f1637ffbc2350b8b3
https://doi.org/10.1109/jssc.2007.908006
https://doi.org/10.1109/jssc.2007.908006
Autor:
Stefan Lammers, Gerhard Müller, R. P. Robertazzi, W. Obermaier, William J. Gallagher, William Robert Reohr, Hans-Heinrich Viehmann, Daniel Braun, C. Arndt, D. Gogl, J. DeBrosse, A. Bette, Heinz Hoenigschmid, R.P. Havreluk, D. Casarotto
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:678-683
A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transisto
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb66c10fa56dc4f37d6218a1498ecf12
https://doi.org/10.1109/jssc.2004.825251
https://doi.org/10.1109/jssc.2004.825251
Autor:
Dietmar Essex Junction Gogl, William Robert Reohr, Yu Lu, Stuart S. P. Parkin, F. Pesavento, William J. Gallagher, G. Muller, C. Arndt, R. Robertazzi, K. Lewis, Hans-Heinrich Viehmann, H. Honigschmid, Li-Kong Wang, Roy Edwin Scheuerlein, Philip L. Trouilloud, S. Lammers
Publikováno v:
IEEE Circuits and Devices Magazine. 18:17-27
With the promise of nonvolatility, practically infinite write endurance, and short read and write times, magnetic tunnel junction magnetic random access memory could become a future mainstream memory technology.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c1fb0afe3b9ce6b53313164e0e57106
https://doi.org/10.1109/mcd.2002.1035347
https://doi.org/10.1109/mcd.2002.1035347
Autor:
William Robert Reohr, Erik A. Nelson, Abraham Mathews, Gregory J. Fredeman, Michael A. Sperling, Charlie Hwang, Kavita Nair, Nianzheng Cao, Don Plass, John E. Barth
Publikováno v:
ISSCC
Logic-based embedded DRAM has matured into a wide range of ASIC applications, SRAM replacements [1] and off-chip caches for microprocessors [2]. While embedded DRAM has been leveraged in supercomputers such as IBM's BlueGene/L [3], it's use has been
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b300e0095100aab3c59915f8a58b499
https://doi.org/10.1109/isscc.2010.5433814
https://doi.org/10.1109/isscc.2010.5433814
Autor:
M. Meterelliyoz, William Robert Reohr, Rajiv V. Joshi, Rouwaida Kanj, Jae-Joon Kim, Kevin J. Nowka, Jente B. Kuang, Sani R. Nassif
Publikováno v:
ISQED
We study the yield of a 65nm SOI eDRAM design. The impact of random dopant fluctuations in the cell and micro sense amp is studied under different systematic corner and device type considerations. Trench capacitor variation effects and yield timing w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2829fed904c62258d0f28e1666439390
https://doi.org/10.1109/isqed.2009.4810292
https://doi.org/10.1109/isqed.2009.4810292
Autor:
Jeremy D. Schaub, Ivan Vo, William Robert Reohr, Kevin J. Nowka, Donald W. Plass, Erik A. Nelson, John E. Barth, Tuyen V. Nguyen, Gary D. Carpenter, Abraham Mathews, T. Kirihata, Fadi H. Gebara, J.B. Kuang
Publikováno v:
ESSCIRC
We present an on-chip word line (WL) dual supply system for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c7cd7688b85297687daf541d6593b56
https://doi.org/10.1109/esscirc.2008.4681793
https://doi.org/10.1109/esscirc.2008.4681793
Autor:
S. S. Iyer, Hien Minh Le, Abraham Mathews, Gregory J. Fredeman, P. Wilcox, Hung Ngo, John E. Barth, Trong V. Luong, R. Freese, Peter Juergen Klim, Erik A. Nelson, G. Koch, John Golz, William Robert Reohr, Hillery C. Hunter, Jente B. Kuang, Paul C. Parries, A. Khargonekar, T. Kirihata, D. Dick
Publikováno v:
2008 IEEE Symposium on VLSI Circuits.
We present a 1 MB cache subsystem that integrates 2 GHz embedded DRAM macros, charge pump circuits, a 4 Kb one-time-programmable ROM, clock multipliers, and built-in self test circuitry, having a 36.5 GB/s peak system data-rate. The eDRAM employs a p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa22d4b318c8e10e90b9dcbeb4834f30
https://doi.org/10.1109/vlsic.2008.4586008
https://doi.org/10.1109/vlsic.2008.4586008
Autor:
J. Griesemer, C. Tanner, William Robert Reohr, John W. Golz, J. Harig, Babar A. Khan, S. S. Iyer, Hyun-Chul Kim, T. Kirihata, Stanley E. Schuster, R.P. Havreluk, John E. Barth, Gregory J. Fredeman, Richard E. Matick, K. Yanagisawa, Paul C. Parries, Hillery C. Hunter
Publikováno v:
ISSCC
A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). The macro was characterized via a test chip fabricated in a 65nm SOI deep-trench
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f885479054fd673652676cdef5d88eff
https://doi.org/10.1109/isscc.2007.373506
https://doi.org/10.1109/isscc.2007.373506