Zobrazeno 1 - 10
of 17
pro vyhledávání: '"William K. Henson"'
Autor:
Michael P. Belyansky, Doug H. Lee, Ming Cai, Stephan Waidmann, Brian J. Greene, Karthik Ramani, Frank D. Tamweber, William K. Henson
Publikováno v:
IEEE Transactions on Electron Devices. 57:1706-1709
Strain effects from stress liners on silicon-on-insulator MOSFETs with high-k dielectric and metal gate (HKMG) are reported. By thoroughly evaluating their impact on drive current, mobility, and threshold voltage, the intrinsic performance gain of st
Autor:
T. Hook, Pavan S. Chinthamanipeta, James Chingwei Li, Richard G. Southwick, Balasubramanian S. Pranatharthi Haran, T. Gow, James H. Stathis, Veeraraghavan S. Basker, Rajesh Sathiyanarayanan, Donald F. Canaperi, C-H. Lin, S. Kanakasabapathy, Zuoguang Liu, F. Chen, A. Bryant, Anita Madan, Leo Tai, Kota V. R. M. Murali, Sanjay Mehta, Yiping Yao, Tenko Yamashita, Mukesh Khare, Huiming Bu, R. Kambhampati, Marinus Hopstaken, Z. Zhu, Shahrukh A. Khan, P. Oldiges, Amit Kumar, William K. Henson, Stephan A. Cohen, Shreesh Narasimha, D. McHerron, Darsen D. Lu, J. Johnson
Publikováno v:
2015 Symposium on VLSI Technology (VLSI Technology).
FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a
Publikováno v:
IEEE Electron Device Letters. 30:1344-1346
The temperature dependence of ring-oscillator delay of high-kappa /metal-gate (HKMG) and poly-Si/SiON technologies are analyzed. HKMG gate stacks drive significantly stronger threshold temperature dependence over poly-Si/SiON. This effect, together w
Autor:
K. Kolvenback, Steven W. Mittl, Dan Mocuta, Fen Chen, Yanfeng Wang, John M. Aitken, M. Shinosky, Roger A. Dufresne, William K. Henson
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
Both MOL PC-CA spacer dielectric and BEOL low-k dielectric breakdown data are commonly convoluted with multiple variables present in the data due to the involvement of many process steps such as lithography, etch, CMP, cleaning, and thin film deposit
Autor:
Christopher S. Putnam, K. Duncan, Lawrence F. Wagner, Yue Liang, Sungjae Lee, Anthony I. Chou, Y. Deng, Murshed M. Chowdhury, Kai Zhao, Brian Johnson, Brian J. Greene, William K. Henson, Rainer Thoma, Dustin K. Slisher, R. Rupani, Scott K. Springer, J. Johnson, D. Daley, C. Wermer, Jean-Olivier Plouchart, Edward P. Maciejewski, Y. Wang, Jie Deng, Hongmei Li, Amit Kumar, Jai-Hoon Sim, Paul A. Hyde, Richard Q. Williams, S.H. Ku, A. Sutton, Shreesh Narasimha, Daeik Daniel Kim
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging devic
Autor:
Henry K. Utomo, T. Okawa, Deleep R. Nair, R. Divakaruni, Qintao Zhang, C. W. Lai, Liyang Song, Shin-Ae Lee, Emmanuel Josse, A. Pofelski, H. Onoda, Yue Liang, Chendong Zhu, X. Wu, William K. Henson, Christian Gruensfelder, Judson R. Holt, R.Q. Williams, Thomas A. Wallner, E. Kaste, Y. M. Lee, J.W. Weijtmans, Brian J. Greene, Melanie J. Sherony, J. Brown
Publikováno v:
Proceedings of Technical Program of 2012 VLSI Technology, System and Application.
The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and le
Autor:
M. Shinosky, Dan Mocuta, Brent A. Anderson, Yun-Yu Wang, F. Chen, John M. Aitken, Kai D. Feng, Steve Mittl, R. Kontra, Ann Swift, Mahender Kumar, Terence Kane, William K. Henson, Yanfeng Wang, Di-an Li, Emily R. Kinser
Publikováno v:
2012 IEEE International Reliability Physics Symposium (IRPS).
The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as meta
Autor:
Anda Mocuta, Anthony I. Chou, Frank D. Tamweber, D. Lea, Jie Deng, J. A. Culp, Nivo Rovedo, H. Trombley, E. J. Nowak, Yue Liang, Woo-Hyeong Lee, K. Rim, B. A. Goplen, Sadanand V. Deshpande, William K. Henson, Brian J. Greene, Xiaojun Yu, Howard S. Landis, Dustin K. Slisher, L. R. Logan, Ming Cai, Oleg Gluschenkov, J. Sim, Paul Chang, Noah Zamdmer
Publikováno v:
2011 International Electron Devices Meeting.
We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minim
Autor:
James H. Stathis, Andreas Kerber, R. Divakaruni, Yue Hu, Hemanth Jagannathan, Dae-Gyu Park, Siddarth A. Krishnan, Richard Carter, Deleep R. Nair, Yun-Yu Wang, Ricardo A. Donaton, William K. Henson, Shahab Siddiqui, Ernest Y. Wu, Murshed M. Chowdhury, Kathy Barla, Huiming Bu, Mukesh Khare, Rohit Pal, J.-P. Han, Matthew W. Stoker, S. Saroop, Sufi Zafar, Michael P. Chudzik, Eduard A. Cartier, X. Chen, Jin Cai, Vamsi Paruchuri, Eric C. Harley, Myung-Hee Na, Dimitris P. Ioannou, Ryosuke Iijima, Min Dai, Kevin McStay, Takashi Ando, Joseph F. Shepard, J. Schaeffer, J-H Lee, Naim Moumen, P. Montanini, Lisa F. Edge, Paul D. Agnello, Shreesh Narasimha, Srikanth Samavedam, Dechao Guo, Unoh Kwon, Dominic J. Schepis, Yue Liang, Martin Ostermayr, S. Inumiya, Thomas A. Wallner, B. Greene, H. Yamasaki, D.P. Prakash, Jaeger Daniel, Stephen W. Bedell, M. Hargrove, Michael A. Gribelyuk, Gauri Karve, Y. Lee, Vijay Narayanan, S. Uchimura, Martin M. Frank
Publikováno v:
2011 International Electron Devices Meeting.
Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafer
Autor:
Herbert L. Ho, Jinping Liu, Paul C. Parries, Norman Robson, Jing Li, Puneet Goyal, S.S. Iyer, Ming Yin, Babar A. Khan, Zhengwen Li, Paul D. Agnello, K. V. Hawkins, Sunfei Fang, T. Weaver, Scott R. Stiffler, Kevin McStay, Rishikesh Krishnan, W. Davies, R. Takalkar, T. Kirihata, Sami Rosenblatt, S. Galis, A. Blauberg, Shreesh Narasimha, Michael P. Chudzik, Amanda L. Tessier, William K. Henson, W. Kong, Edward P. Maciejewski, Alberto Cestero, Nauman Zafar Butt, Joseph Ervin, S. Gupta, Jeyaraj Antony Johnson, S. Rombawa, Sungjae Lee, J. Barth, Ying Zhang
Publikováno v:
2010 International Electron Devices Meeting.
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovat