Zobrazeno 1 - 10
of 15
pro vyhledávání: '"William G. En"'
Autor:
Nathan W. Cheung, Lucia Feng, William G. En, Michael A. Bryan, Wei Liu, Shu Qin, Michael I Current, Chung Chan, Ian S. Roth, Francois J. Henley, Albert Lamm, Igor J. Malik
Publikováno v:
Surface and Coatings Technology. 136:138-141
A plasma immersion ion implantation (PIII) system is described which provides the capability to bridge the range between research exploration and commercial applications for materials modification of electronic materials, with a particular focus on l
Publikováno v:
Surface and Coatings Technology. 85:64-69
The effects of wafer bias and plasma parameters on thin oxide charging during plasma immersion ion implantation (PIII) are simulated. The simulator has been shown to determine accurately the charging currents generated during PIII. The dependence of
Autor:
William G. En, Nathan W. Cheung
Publikováno v:
Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms. 96:435-439
The charging effects of plasma immersion ion implantation on several device structures is simulated. The simulations use an analytical model which couples the interaction of the plasma and IC devices during plasma implantation. The plasma model is im
Autor:
Darin Chan, Gert Burbach, C. Lee, R. vanBentum, D. Greenlaw, A. Wei, Dong-Hyuk Ju, S. Krishnan, N. Kepler, Mario M. Pelella, M. Fuselier, D. Wristers, C. Riccobenc, M. Lee, G. Hill, D. Wu, S. Chan, Ping Yeh, S. R. Sundararajan, W. Maszara, S. Sinha, William G. En, Olov Karlsson
Publikováno v:
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
The key performance advantages and challenges of SOI CMOS for ULSI applications are discussed in detail. Included is an insightful analysis comparing the performance benefits of SOI technologies over its bulk-Si counterpart. The hysteretic trends of
Publikováno v:
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
Stress from shallow trench isolation was found to cause up to 19% variation in 0.18 /spl mu/m technology SO! devices. Partially depleted SOI devices were fabricated on a 0.18 /spl mu/m technology with 100 nm thick silicon film and 200 nm thick buried
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 20:640
Deep submicron transistor source–drain structures require a challenging combination of ultrashallow depth and low series resistance. Because these factors affect off-state leakage, drive current, and threshold voltage, it is important to maintain t
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 14:552
An analytical model of oxide charging in plasma processing is presented. The model simulates the interactions of the plasma with semiconductor device structures on the wafer and the substrate bias to determine the charging induced in thin gate oxides
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 12:956
Plasma immersion ion implantation (PIII) with BF3 and SiF4 plasmas is used to fabricate shallow P+/N junctions in Si. Exposure to the plasma and accelerated ions can lead to simultaneous etching and deposition on the substrate during implantation. A
Autor:
Nathan W. Cheung, William G. En
Publikováno v:
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures. 12:833
Plasma immersion ion implantation applies a series of negative high‐voltage pulses to a target immersed in a plasma. An analytical model of the currents and potentials induced before, during, and after the negative bias in a planar geometry is pres
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